Diodes Incorporated PI6CB18801ZLIEX-13R

Overview

PI6CB18801ZLIEX-13R from Diodes Incorporated is a very low power 8-output PCIe Gen1–Gen4 clock buffer with integrated HCSL output termination, 1.8V supply, and programmable slew rate/amplitude per output. It accepts a differential HCSL input (100/50/125 MHz), locks via proprietary PLL, and delivers eight low-jitter differential outputs with individual OE# control - used in high-speed server motherboard clock distribution.

For engineers reviewing the PI6CB18801ZLIEX-13R datasheet, PI6CB18801ZLIEX-13R pinout, PI6CB18801ZLIEX-13R application, or PI6CB18801ZLIEX-13R equivalent, key selection criteria include PCIe Gen4-compliant jitter (<50 ps cycle-to-cycle), on-chip 85Ω HCSL termination saving 32 external resistors, SMBus-configurable frequency/slew/amplitude, and industrial-grade –40°C to +85°C operation.

Technical Context

The device implements a proprietary low-jitter PLL architecture with selectable loop bandwidth (1–4 MHz) and optional bypass mode for deterministic latency. Input-to-output propagation delay is <200 ps in PLL mode and 3.0–4.5 ns in bypass mode, enabling timing-critical PCIe root complex and switch fanout.

All eight HCSL outputs feature independent enable/disable control via dedicated OE# pins and SMBus registers, while tri-level strapping pins (SADR_TRI, BW_SEL_TRI) allow hardware configuration without firmware. The 3.3V-tolerant SMBus interface supports block read/write at up to 400 kHz for dynamic reconfiguration during system boot or thermal management.

Key Specifications

Pinout & Package

PI6CB18801ZLIEX-13R uses a 48-lead 6×6 mm TQFN package with exposed thermal pad (EPAD). Pin layout separates analog (VDDA/GNDA), digital (VDD_DIG/GND_DIG), input (VDD_R/GND_R), and output (VDDO/GND) power domains to minimize noise coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242B and ICS843002AGI-01LFT, PI6CB18801ZLIEX-13R uniquely combines on-chip HCSL termination, SMBus-programmable frequency/slew/amplitude, and individual OE# control - delivering lower BOM cost, smaller footprint, and superior thermal/power scalability in Gen4+ server and networking platforms.

Availability

PI6CB18801ZLIEX-13R is available at Aetrix Electronics and suitable for PCIe Gen4 server motherboards, enterprise NVMe storage controllers, and 5G fronthaul baseband units requiring stable component supply, long-term lifecycle support, and RoHS-compliant green packaging.

Supply support for PI6CB18801ZLIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for power management, signal integrity, and connectivity applications.

The PI6CB18801 belongs to Diodes' high-performance clock buffer product line, engineered specifically for PCIe Gen1–Gen4, Ethernet, and CPRI timing distribution in data center, telecom, and enterprise storage systems.

FAQ

What is the minimum input voltage swing required for reliable locking?

The PI6CB18801ZLIEX-13R requires a differential input swing of ≥300 mV_PP (typical 1450 mV_PP) with common-mode voltage between 150 mV and 1000 mV. At 100 MHz, it locks reliably with 600–1150 mV single-ended high and –300–300 mV low levels on IN+/IN−, verified across –40°C to +85°C.

How does the on-chip termination affect signal integrity compared to external resistors?

On-chip 85Ω HCSL termination provides tighter impedance matching (±5%) versus typical ±10% tolerance of 0402 external resistors, reducing reflection-induced jitter by up to 12 ps. It also eliminates stub effects from resistor pads, improving eye height by 8% at 16 GT/s in 4-inch FR4 traces.

Can the SMBus interface be used during normal operation without disrupting clock outputs?

Yes - SMBus transactions do not interrupt clock outputs. Register writes to Byte 0 (OE control) or Byte 2 (slew rate) take effect within 3 clock cycles, and all timing parameters (jitter, skew, duty cycle) remain within spec during and after configuration changes.

What is the power-up sequence requirement for guaranteed initialization?

No strict power sequencing is required. All supplies (VDD, VDD_DIG, VDD_R, VDDA, VDDO) may ramp simultaneously. The device enters functional state within 10 ms of VDD reaching 1.7 V, and PLL locks within 20 ms of stable input clock presence - verified across full temperature and voltage ranges.