Diodes Incorporated PI6CB33202ZDIEX-13R

Overview

PI6CB33202ZDIEX-13R from Diodes Incorporated is a very-low-power, two-output PCIe clock buffer with integrated PLL and on-chip 85Ω HCSL termination. It supports 50/100/125/133.33MHz input frequencies, delivers differential cycle-to-cycle jitter <50ps, meets PCIe Gen1–Gen5 CC compliance, and operates across –40°C to +85°C for industrial server and storage applications.

For engineers reviewing the PI6CB33202ZDIEX-13R datasheet, PI6CB33202ZDIEX-13R pinout, PI6CB33202ZDIEX-13R application, or PI6CB33202ZDIEX-13R equivalent, key selection criteria include PCIe Gen5-compliant additive jitter (≤0.15ps RMS), individual output enable (OE0#/OE1#), SMBus-configurable slew rate/amplitude, and 24-pin 4mm × 4mm TQFN packaging with exposed pad.

Technical Context

The PI6CB33202 implements a proprietary low-jitter PLL architecture with selectable loop bandwidth (0.7–3.6MHz) and optional bypass mode, enabling deterministic phase alignment and spread-spectrum tolerance. Its dual HCSL outputs feature independent enable control, programmable amplitude (0.6–0.85V), and slew rate tuning via SMBus or strapping pins.

Input accepts differential HCSL at 100MHz (PCIe default) or 50/125/133.33MHz via SMBus configuration; outputs drive 5-inch traces with <50ps output-to-output skew and <11ps typical duty-cycle distortion in PLL mode. Power management includes PD#-controlled shutdown with <2mA total supply current in power-down state.

Key Specifications

Pinout & Package

Package: 24-lead 4mm × 4mm TQFN with exposed thermal pad (EPAD), RoHS-compliant and halogen-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242B and Si53302-A01AM, the PI6CB33202ZDIEX-13R uniquely balances PCIe Gen5 compliance, on-chip 85Ω termination, SMBus-reconfigurable frequency/amplitude, and 44mA power consumption - making it optimal for cost-sensitive, space-constrained industrial and server clock trees where flexibility and Gen5 readiness are prioritized over multi-protocol support or sub-0.1ps jitter.

Availability

PI6CB33202ZDIEX-13R is available at Aetrix Electronics and suitable for PCIe Gen5 server backplanes, enterprise NVMe SSD controllers, 5G O-RAN baseband units, and industrial Ethernet switches requiring stable component supply, long-term lifecycle assurance, and RoHS 3/Green compliance.

Supply support for PI6CB33202ZDIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for industrial, computing, and communications markets.

The PI6CB33202 belongs to Diodes' PCIe-optimized clock buffer product line, designed specifically to reduce BOM count and layout complexity in high-density server, storage, and 5G infrastructure while meeting stringent Gen5 jitter and power targets.

FAQ

What is the minimum input frequency supported by the PI6CB33202ZDIEX-13R in PLL mode?

The device supports 50MHz as the lowest input frequency in PLL mode, confirmed by the Frequency Select Table (Byte3[4:3] = 01). At 50MHz, both outputs deliver synchronized 50MHz HCSL signals with <50ps cycle-to-cycle jitter and full SMBus configurability for amplitude and slew rate - validated for 2.5G Ethernet PHY timing applications.

How does the on-chip 85Ω termination affect PCB layout compared to discrete termination?

The integrated 85Ω differential termination eliminates eight external 42.5Ω resistors (four per output), reducing component count, saving ≥12mm² board area per output, and removing stub-induced reflections from resistor pads. Layout benefits include shorter trace lengths, improved signal integrity at 100MHz+, and simplified routing for tight-pitch PCIe connectors - verified in Diodes' reference design RD-PI6CB33202.

Can the PI6CB33202ZDIEX-13R operate in PLL bypass mode, and what are the timing implications?

Yes - BW_SEL_TRI strapping or SMBus Byte1[7:6] selects PLL bypass mode, disabling the PLL and passing input directly to outputs with 2–3ns propagation delay. In this mode, additive jitter drops to ≤1ps RMS, but frequency flexibility is limited to the input source; duty-cycle distortion remains <±3.5% at 100MHz, making it ideal for legacy PCIe Gen1–3 systems with stable reference clocks.

What is the maximum SMBus clock frequency supported, and how is bus reliability ensured?

The PI6CB33202ZDIEX-13R supports SMBus up to 500kHz, with rise/fall time limits of 1000ns/300ns and VIH/VIL thresholds defined for 2.7–3.6V VDDSMB. Bus reliability is enhanced by 2000V HBM ESD protection on SDATA/SCLK, internal weak pullup/pulldown on control pins, and block-read/write protocol with ACK/NACK handshaking - ensuring robust configuration in noisy industrial environments.