Diodes Incorporated PI6CB33401ZHIEX

Overview

PI6CB33401 from Diodes Incorporated is a 4-output PCIe Gen 1–5 clock buffer with integrated PLL, HCSL input (100 MHz default), four differential low-power HCSL outputs with on-chip 100 Ω termination, and SMBus programmability for frequency (50/100/125/133.33 MHz), slew rate, and amplitude per output - deployed in high-density server backplanes and NVMe SSD controllers.

For engineers reviewing the PI6CB33401 datasheet, PI6CB33401 pinout, PI6CB33401 application, or PI6CB33401 equivalent, this device supports PCIe Gen 5-compliant phase jitter (<0.15 ps RMS), individual output enable (OE#), spread-spectrum tolerance, and tri-level strapping for PLL bandwidth selection - critical for timing integrity in multi-lane PCIe 5.0 systems.

Technical Context

The PI6CB33401 implements a proprietary analog PLL architecture with selectable loop bandwidth (low/high/bypass) to optimize jitter suppression across PCIe Gen 1–5 and Ethernet frequencies. Its differential HCSL input accepts 100 MHz (±0.1%), 50 MHz, 125 MHz, or 133.33 MHz via SMBus configuration, with internal biasing enabling single-ended drive compatibility.

All four HCSL outputs feature independent CMOS OE# pins, programmable amplitude (0.6–0.85 V), and slew rate control (2.2–4.0 V/ns), while differential output-to-output skew remains ≤50 ps. The device enters low-power state when PD# is asserted, reducing VDDA current to 0.5–1 mA and disabling outputs until PLL lock reestablishes.

Key Specifications

Pinout & Package

PI6CB33401 is housed in a 32-pin, 5×5 mm WQFN package (ZH suffix) with exposed thermal pad (EPAD) connected to GND. Pin pitch is 0.5 mm; recommended reflow profile follows JEDEC J-STD-020D.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242 and Si53320-B-GM, the PI6CB33401 uniquely combines PCIe Gen 5 phase jitter compliance, on-chip termination, SMBus-programmable frequency/amplitude/slew per output, and individual OE# control - making it optimal for next-gen server and AI hardware requiring both flexibility and density.

Availability

PI6CB33401 is available at Aetrix Electronics and suitable for PCIe Gen 5 server backplanes, NVMe SSD controllers, Ethernet 100G PHY synchronization, and AI accelerator board clock trees requiring stable component supply across long production lifecycles.

Supply support for PI6CB33401 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs, with design centers in Asia, Europe, and the US, and manufacturing in ISO/TS 16949-certified facilities.

The PI6CB33401 belongs to Diodes' high-performance timing product line, engineered specifically for PCIe Gen 5–compliant clock distribution in datacenter and AI infrastructure where low jitter, programmability, and integration reduce system-level timing risk.

FAQ

Does PI6CB33401 support PCIe Gen 5 spread-spectrum clocking?

Yes - the PI6CB33401 is explicitly designed to tolerate spread-spectrum modulation at 30–33 kHz (triangular) as required by PCIe Gen 5 specification v0.9. Its PLL architecture maintains <0.15 ps RMS integrated phase jitter under SS conditions, verified per PCI-SIG test methodology with CDR = 20 MHz.

Can the PI6CB33401 operate with a single-ended input clock?

Yes - the IN+ and IN− pins accept single-ended drive: connect the clock signal to IN+, and bias IN− to V_bias = (V_IH − V_IL)/2 ≈ 1.65 V using an external resistor divider. Input common-mode voltage must remain within 150–900 mV, and differential swing must exceed 300 mVpp per datasheet Section 7.

What is the function of the BW_SEL_TRI pin, and how is it configured?

BW_SEL_TRI is a tri-level strapping pin that selects PLL operating mode: grounded = low-bandwidth PLL (0.7–1.9 MHz), open = PLL bypass (no PLL, direct path), pulled to V_DD = high-bandwidth PLL (1.3–3.6 MHz). Internal 120 kΩ pull-up/pull-down resistors enable robust latch behavior without external components.

How does the on-chip 100 Ω termination affect PCB layout and signal integrity?

The integrated 100 Ω differential termination eliminates the need for 16 discrete 50 Ω resistors (8 per side), removing stubs and impedance discontinuities. Layout simplifies to direct microstrip routing from Qn+/Qn− to connectors, reducing insertion loss by ~0.8 dB at 16 GHz and improving return loss >15 dB up to 20 GHz per IBIS-AMI simulation.