Diodes Incorporated PI6CB33402ZHIEX-13R

Overview

PI6CB33402ZHIEX-13R from Diodes Incorporated is a 4-output PCIe Gen 1–5 clock buffer with integrated HCSL input and on-chip 85Ω termination, operating at 3.3V supply, delivering <50ps differential cycle-to-cycle jitter and supporting 50/100/125/133.33MHz frequencies via SMBus configuration for server, storage, and networking applications.

For engineers reviewing the PI6CB33402ZHIEX-13R datasheet, PI6CB33402ZHIEX-13R pinout, PI6CB33402ZHIEX-13R application, or PI6CB33402ZHIEX-13R equivalent, key selection criteria include PCIe Gen 5 phase jitter compliance (≤0.15ps RMS), individual output enable control (OE0#–OE3#), programmable slew rate per output, spread-spectrum tolerance, and 32-pin TQFN package with internal PLL bandwidth selection.

Technical Context

The device implements a proprietary low-jitter PLL architecture with selectable loop bandwidth (0.7–3.6 MHz) and bypass mode, enabling deterministic timing alignment across four HCSL outputs. Input accepts differential HCSL at 100MHz (PCIe default) or 50/125/133.33MHz via SMBus register Byte 3.

Configuration is supported via tri-level strapping pins (BW_SEL_TRI, SADR_TRI) and SMBus interface (SCLK/SDATA), allowing runtime adjustment of output amplitude (0.6–0.85V), slew rate (2.2–4.0 V/ns), and frequency select-without requiring external resistors due to on-chip 85Ω termination per output pair.

Key Specifications

Pinout & Package

Package: 32-contact, 5mm × 5mm TQFN (W-QFN5050-32), lead-free and RoHS-compliant, with exposed EPAD connected to GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242A and Si53302-A01AGM, PI6CB33402ZHIEX-13R uniquely combines on-chip 85Ω termination, per-output SMBus-adjustable amplitude/slew, and PCIe Gen 5 jitter compliance in a compact 5×5mm package-reducing component count and enabling dynamic power management unattainable with fixed-function alternatives.

Availability

PI6CB33402ZHIEX-13R is available at Aetrix Electronics and suitable for PCIe Gen 5 server backplanes, enterprise SSD controllers, 5G fronthaul cards, and AI accelerator mezzanines requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for PI6CB33402ZHIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and ICs, specializing in high-performance timing, power management, and signal integrity solutions for computing, communications, and industrial markets.

The PI6CB33402 belongs to Diodes' PCIe-optimized clock buffer product line, designed specifically to meet Gen 5 jitter, skew, and configurability requirements while minimizing external components and PCB footprint in high-speed data center applications.

FAQ

What is the default output frequency and how is it changed?

The default output frequency is 100MHz, matching PCIe Gen 1–5 reference clock requirements. It can be changed to 50MHz, 125MHz, or 133.33MHz by setting bits FSEL1/FSEL0 in SMBus register Byte 3 after enabling FREQ_SEL_EN. Strapping pins do not support frequency selection-only SMBus configuration enables non-default frequencies.

Does PI6CB33402ZHIEX-13R require external termination resistors?

No. The device integrates 85Ω on-chip termination for each HCSL output pair (Q0+/- through Q3+/-), eliminating the need for 16 external 85Ω resistors. This reduces PCB layout complexity, saves board space, and improves signal integrity by removing stubs and parasitic inductance associated with discrete terminations.

How does the BW_SEL_TRI pin affect PLL performance?

BW_SEL_TRI is a tri-level input that selects PLL operating mode: logic low enables low-bandwidth mode (0.7–1.9MHz), mid-level bypasses the PLL entirely, and high level enables high-bandwidth mode (1.3–3.6MHz). Bandwidth selection directly impacts jitter filtering-low BW suppresses high-frequency noise but increases lock time; high BW improves transient response but passes more reference jitter.

Can all four outputs operate at different frequencies simultaneously?

No. All four outputs share the same frequency source-either the input clock (in PLL bypass mode) or the PLL output (in PLL mode). SMBus frequency selection applies globally; there is no per-output frequency programming. However, each output can be independently enabled/disabled and configured for unique slew rate and amplitude settings.