Diodes Incorporated PI6CB33601ZLAIEX

Overview

PI6CB33601 from Diodes Incorporated is a 6-output PCIe Gen1–Gen5 clock buffer with HCSL input and six low-power differential HCSL outputs, on-chip 100Ω termination, SMBus programmability, and individual output enable control. It operates at 3.3V supply, supports 50/100/125/133.33MHz frequencies, and delivers <50ps differential cycle-to-cycle jitter for high-speed server and storage applications.

For engineers reviewing the PI6CB33601 datasheet, PI6CB33601 pinout, PI6CB33601 application, or PI6CB33601 equivalent, this device is selected for PCIe timing fanout where low jitter, spread-spectrum tolerance, per-output power management, and layout simplification via integrated termination are critical design requirements.

Technical Context

The PI6CB33601 employs a proprietary low-jitter PLL architecture with selectable loop bandwidth (0.7–3.6 MHz) and optional PLL bypass mode, enabling deterministic phase alignment and jitter filtering across PCIe Gen1–Gen5 compliance bands. Its dual-mode operation supports both locked-PLL timing distribution and direct pass-through for ultra-low latency.

It integrates tri-level strapping pins (SADR_TRI, BW_SEL_TRI) and full SMBus register access (7-byte address space) for dynamic configuration of output amplitude (0.6–0.85V), slew rate (2.2–4.0 V/ns), frequency selection, and output enable states - all without requiring external pull resistors due to internal 120kΩ pull-up/down networks.

Key Specifications

Pinout & Package

Package: 40-lead 5×5 mm TQFN (exposed pad grounded), RoHS-compliant and halogen-free "Green" construction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242A and Si53307-A01AGM, the PI6CB33601 uniquely combines on-chip termination, per-output SMBus-configurable amplitude/slew rate, and PCIe Gen5-compliant jitter in a compact 5×5 mm TQFN - delivering superior layout efficiency and dynamic timing optimization for next-gen compute platforms.

Availability

PI6CB33601 is available at Aetrix Electronics and suitable for PCIe Gen5 server backplanes, enterprise SSD controllers, AI accelerator boards, and 5G fronthaul systems requiring stable component supply, long-term lifecycle assurance, and automotive-grade change control readiness.

Supply support for PI6CB33601 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of high-performance analog and mixed-signal semiconductors, specializing in precision timing, power management, and signal integrity solutions for computing, communications, and industrial markets.

The PI6CB33601 belongs to Diodes' PCIe-optimized clock buffer product line, engineered specifically for high-density, low-power, Gen5-ready timing distribution in servers, storage, and AI infrastructure where jitter, layout simplicity, and configurability are critical.

FAQ

What is the minimum input swing required for reliable operation of the PI6CB33601?

The PI6CB33601 requires a differential input swing of 300 mV_PP minimum (typical 2900 mV_PP) across IN+/IN−, with common-mode voltage between 150 mV and 900 mV. Input duty cycle must be 45–55%, and slew rate ≥0.4 V/ns. These values ensure robust PLL locking and jitter performance across PCIe Gen1–Gen5 frequencies.

How does the PI6CB33601 handle power-down sequencing with respect to output state?

When PD# is pulled low, all outputs transition to LOW/LOW state within 300 µs, analog and digital supplies draw <2 mA total, and the PLL stops. Upon PD# de-assertion, outputs remain disabled until PLL lock is achieved (~1 ms), preventing glitch propagation. OE# pins retain their prior state but are overridden during power-down.

Can the PI6CB33601 operate with a single-ended input clock?

Yes - the device accepts single-ended input by driving IN+ with the clock signal and biasing IN− to V_Bias = (V_IH − V_IL)/2 ≈ 1.65 V. This configuration maintains valid common-mode range and preserves jitter performance, though differential input is preferred for optimal noise immunity and cycle-to-cycle jitter.

What is the maximum allowable SMBus clock frequency and rise/fall time for reliable register access?

The PI6CB33601 supports SMBus up to 500 kHz with rise time ≤1000 ns and fall time ≤300 ns. VIH must exceed 2.1 V (at 3.3 V bus), VIL must stay below 0.8 V, and sink current capability is 4 mA. Exceeding these limits risks register write failures or unintended configuration changes during hot-plug events.