Diodes Incorporated PI6CB33602ZLAIEX-13R

Overview

PI6CB33602ZLAIEX-13R from Diodes Incorporated is a 6-output PCIe Gen1–Gen5 clock buffer with integrated PLL, HCSL differential I/O, on-chip 85Ω termination, and SMBus programmability. It accepts 100MHz (also 50/125/133.33MHz) differential input and delivers six low-jitter, individually enabled HCSL outputs for high-speed serial interconnects in server, storage, and AI accelerator platforms.

For engineers reviewing the PI6CB33602ZLAIEX-13R datasheet, PI6CB33602ZLAIEX-13R pinout, PI6CB33602ZLAIEX-13R application, or PI6CB33602ZLAIEX-13R equivalent, key selection criteria include PCIe Gen5-compliant additive jitter (<0.15ps RMS), differential output-to-output skew <50ps, individual OE# control per output, SMBus-configurable slew rate/amplitude, and 40-pin 5×5mm TQFN package with internal pull-up/down strapping pins.

Technical Context

The PI6CB33602ZLAIEX-13R implements a proprietary low-noise PLL architecture with selectable loop bandwidth (0.7–3.6MHz) to meet PCIe Gen1–Gen5 phase jitter requirements across all data rates. Its differential HCSL outputs feature programmable amplitude (0.6V–0.85V) and slew rate (2.2–4.0 V/ns), with output state held low until PLL lock detection.

Configuration is supported via tri-level strapping pins (SADR_TRI, BW_SEL_TRI) or SMBus interface (block read/write, 7-bit address), enabling dynamic frequency selection (50/100/125/133.33MHz), per-output enable/disable, and power-down mode entry via PD# assertion. All outputs are terminated on-die to eliminate 24 external resistors.

Key Specifications

Pinout & Package

PI6CB33602ZLAIEX-13R is housed in a 40-lead, 5×5mm, 0.5mm pitch TQFN package with exposed thermal pad (EPAD) connected to GND. Pin functions are validated per Diodes DS41291 Rev 6-2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242A and Si53306-A01AGM, the PI6CB33602ZLAIEX-13R uniquely combines PCIe Gen5 compliance, on-die 85Ω termination, per-output enable, and SMBus-driven amplitude/slew tuning - reducing component count and enabling adaptive signal integrity optimization in dense, multi-standard systems.

Availability

PI6CB33602ZLAIEX-13R is available at Aetrix Electronics and suitable for PCIe Gen5 server backplanes, AI accelerator timing hubs, Ethernet 25G/100G line cards, and enterprise NVMe storage controllers requiring stable component supply and long-term lifecycle support.

Supply support for PI6CB33602ZLAIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-performance timing, power management, and signal integrity solutions for industrial, computing, and communications markets.

The PI6CB33602 belongs to Diodes' PCIe-optimized clock buffer product line, engineered specifically to replace legacy fanout buffers in Gen4/Gen5 infrastructure with lower power, higher integration, and enhanced programmability for next-generation data center hardware.

FAQ

What is the minimum input clock frequency supported in PLL mode?

The PI6CB33602ZLAIEX-13R supports 50MHz, 100MHz, 125MHz, and 133.33MHz input frequencies in PLL mode, with 50MHz being the lowest confirmed operational frequency per DS41291 Rev 6-2. Input frequencies below 50MHz are not characterized or guaranteed, and the device will not lock or generate valid outputs outside this range.

How does the on-chip 85Ω termination affect PCB layout compared to external termination?

The integrated 85Ω differential termination eliminates the need for 24 discrete 42.5Ω resistors (12 per side), removing associated routing stubs, pad capacitance, and placement constraints. This reduces total clock net impedance discontinuity by up to 15%, improves return loss above 8GHz, and enables direct microstrip routing from Qn+/Qn- pins to connector or ASIC without intermediate termination pads.

Can the SMBus interface be used while the device is operating in PLL bypass mode?

Yes - SMBus communication remains fully functional in PLL bypass mode. The SMBus controller can read status registers (e.g., PLL lock flag in Byte1), modify output enable states (Byte0), adjust amplitude/slew rate (Bytes1–2), and change frequency selection (Byte3) without disrupting the bypassed clock path or requiring device reset.

What is the maximum allowable propagation delay variation across all six outputs?

The differential output-to-output skew is specified as ≤50ps (typ. 21ps) under standard conditions (TA = 25°C, VDD = 3.3V, 100MHz). This includes worst-case process/voltage/temperature variation and applies to all six Qn+/Qn- pairs simultaneously - ensuring deterministic timing alignment critical for multi-lane PCIe Gen5 x16 and NVLink 4.0 implementations.