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Diodes Incorporated PI6CB33801ZLIEX
- Part No.:
- PI6CB33801ZLIEX
- Manufacturer:
- Diodes Incorporated
- Category:
- Clock Buffers, Drivers
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
PI6CB33801ZLIEX.pdf
- Description:
- IC CLK BUF 1:8 133.33MHZ 48TQFN
- Quantity:
- Payment:
- Shipping:
Inventory:8,442
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Product details
Overview
PI6CB33801 from Diodes Incorporated is a very-low-power 8-output PCIe clock buffer with on-chip 100Ω HCSL termination, supporting PCIe Gen1–Gen5 (100MHz), Ethernet (50/125/133.33MHz), and spread-spectrum tolerant operation. It features individual output enable pins, programmable slew rate and amplitude per output, and differential output-to-output skew <50ps.
For engineers reviewing the PI6CB33801 datasheet, PI6CB33801 pinout, PI6CB33801 application, or PI6CB33801 equivalent, this device is selected for high-density server backplanes, NVMe SSD controllers, multi-lane PCIe switch fanout, and low-jitter timing distribution where external termination reduction and SMBus configurability are critical.
Technical Context
The PI6CB33801 integrates a proprietary low-jitter PLL with selectable loop bandwidth (0.7–3.6 MHz) and optional bypass mode, enabling compliance with PCIe Gen1–Gen5 phase jitter limits (≤0.15 ps RMS for Gen5). Its HCSL outputs drive 5-inch traces with default 100Ω on-die termination, eliminating 32 external resistors.
Configuration is supported via tri-level strapping pins (SADR_TRI, BW_SEL_TRI) or SMBus interface (3.3V-tolerant, up to 500 kHz), allowing runtime adjustment of output amplitude (0.6–0.85 V), slew rate (2.2–4.0 V/ns), and frequency selection across four input standards.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 8 differential HCSL outputs with independent OE# control |
| Input frequency support | 100 MHz (PCIe Gen1–Gen5), plus 50/125/133.33 MHz for Ethernet |
| Differential cycle-to-cycle jitter | <50 ps (typ. 14 ps) in PLL mode - meets PCIe Gen5 SRiS/SRnS |
| On-chip termination | 100 Ω per output pair - eliminates 32 external 50 Ω resistors |
| Supply voltage | VDD = 3.3 V ±4.5%; VDDO = 0.95–3.465 V - supports flexible I/O voltage scaling |
| Power-down current | IDDO_PD = 0.04–0.1 mA - enables ultra-low standby power in idle lanes |
| SMBus interface | 3.3 V-tolerant, 500 kHz max - enables dynamic output tuning without hardware change |
Pinout & Package
Package: 48-lead 6 mm × 6 mm TQFN with exposed thermal pad (EPAD) connected to GND.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN+, IN− | Differential HCSL clock input | Accepts 100/50/125/133.33 MHz; common-mode range 150–900 mV |
| Q0+ to Q7+ | Differential true outputs | HCSL-compliant; VOH = 660–850 mV, VOL = −150–150 mV |
| Q0− to Q7− | Differential complementary outputs | Matched slew rate (±15%) and skew (<50 ps) across all 8 pairs |
| OE0# to OE7# | Active-low CMOS output enables | Internal pull-down; overrides SMBus register control when asserted |
| SADR_TRI, BW_SEL_TRI | Tri-level configuration latches | Set SMBus address and PLL bandwidth mode at power-up; no external logic needed |
| PD# | Power-down control | Internal pull-up; deassertion enables outputs after 20–300 µs stabilization |
Key Features
| Feature | Design Value |
|---|---|
| Per-output amplitude programming | Four settings (0.6 / 0.68 / 0.75 / 0.85 V) via SMBus Byte 1 - optimizes signal integrity per lane |
| Per-output slew rate control | Fast/slow modes (2.2–4.0 V/ns) via SMBus Byte 2 - reduces EMI on sensitive routing layers |
| Differential output blocking | Outputs held low until PLL lock detected - prevents metastable clock propagation during startup |
| Spread spectrum tolerance | Supports 30–33 kHz triangular modulation (PCIe) and 0–46 kHz (non-PCIe) - maintains timing margin under SS clocking |
| Low-power operation | Total IDD = 34–40 mA @ 100 MHz; IDDO_PD = 0.04–0.1 mA in power-down - extends system-level energy efficiency |
Applications
| PCIe Gen5 Server Backplane | NVMe SSD Controller Fanout |
|---|---|
Use Scenario: Distributing 100 MHz reference clock across 8 PCIe Gen5 x4 lanes in a 2U rack server backplane with tight trace length matching. IC Role / Device Role / Timing Role: Low-jitter clock fanout buffer with on-chip 100Ω termination and <50 ps output skew - replaces discrete resistor networks and reduces layout complexity. Use Value: Eliminates 32 external termination resistors, cuts PCB area by ≥12 mm² per output pair, and ensures PCIe Gen5 CC compliance with <0.15 ps RMS additive jitter. | Use Scenario: Driving eight HCSL clock inputs on dual-controller NVMe SSD modules requiring independent lane enable/disable for power gating. IC Role / Device Role / Timing Role: Individually enabled 8-output buffer with SMBus-configurable amplitude and slew rate - enables per-lane optimization for varying trace lengths and loading. Use Value: Reduces inter-lane duty cycle distortion to <3.5% and supports dynamic amplitude tuning (0.6–0.85 V) to match controller input thresholds without board respins. |
| Ethernet Switch Timing Module | Multi-Protocol FPGA Clock Distribution |
Use Scenario: Providing synchronized 125 MHz clocks to eight 25G Ethernet PHYs in a layer-3 switch ASIC carrier board. IC Role / Device Role / Timing Role: Programmable-frequency clock buffer supporting 50/125/133.33 MHz via SMBus - enables single BOM for multiple Ethernet standards. Use Value: Achieves 0.15–0.3 ps RMS integrated phase jitter at 125/133.33 MHz, meeting IEEE 802.3bj KR/KP jitter budgets without external filtering. | Use Scenario: Feeding clock domains to heterogeneous FPGA peripherals including PCIe, DDR4, and 10GbE MACs from one compact timing source. IC Role / Device Role / Timing Role: Multi-standard clock buffer with strappable PLL mode (bypass/high/low BW) and SMBus reconfiguration - simplifies timing architecture across mixed-speed interfaces. Use Value: Enables runtime switching between PCIe Gen4 (high-BW PLL) and DDR4 (low-BW PLL) modes while maintaining <50 ps cycle-to-cycle jitter in both configurations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PCIe clock buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ICS843002AGI-01LFT | 8-output LVDS buffer; requires external 100Ω termination; no SMBus programmability | Limited to fixed 100 MHz; no Ethernet frequency support or per-output control | Choose only if LVDS interface and static configuration are acceptable and PCB space allows external resistors. |
| PI6C557-03LEX | 8-output HCSL buffer with fixed 100Ω termination; no PLL - only bypass mode; no SMBus | No frequency flexibility (100 MHz only); no jitter cleanup; higher additive jitter (1 ps vs. 0.15 ps) | Select only for cost-sensitive Gen3/Gen4 designs where PLL jitter suppression is not required. |
Compared with ICS843002AGI-01LFT and PI6C557-03LEX, the PI6CB33801 uniquely combines on-chip termination, PCIe Gen5-compliant jitter performance, SMBus-based per-output tuning, and multi-frequency support - making it the only option for scalable, future-proof, high-density PCIe timing architectures.
Availability
PI6CB33801 is available at Aetrix Electronics and suitable for PCIe Gen5 server backplanes, NVMe SSD controller fanout, and Ethernet switch timing modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant green packaging.
Supply support for PI6CB33801 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, communications, and industrial markets.
The PI6CB33801 belongs to Diodes' PCIe-optimized clock buffer product line, designed specifically to reduce system-level timing complexity in high-speed serial interconnects through integrated termination, ultra-low jitter, and flexible configuration.
FAQ
What is the minimum input clock slew rate supported by the PI6CB33801?
The PI6CB33801 specifies a minimum differential input slew rate of 0.4 V/ns, measured across a ±75 mV window centered at differential zero. This ensures reliable locking for standard HCSL and LVDS sources, and the device also accepts single-ended inputs biased at mid-supply (Vbias = (VIH−VIL)/2) per datasheet note 3.
How does the PI6CB33801 handle power sequencing across its multiple supply domains?
The PI6CB33801 has five independent supply domains: VDD (core), VDD_DIG (digital), VDD_R (input buffers), VDDA (analog), and VDDO (outputs). All supplies must be within specification before PD# deassertion; no strict ramp-order dependency is required, but VDDO must stabilize before outputs become active (tPDLAT = 20–300 µs after PD# high).
Can the PI6CB33801 operate without an SMBus host controller?
Yes. Configuration is fully supported via tri-level strapping pins SADR_TRI and BW_SEL_TRI at power-up. SMBus is optional for runtime reconfiguration - e.g., changing output amplitude or slew rate during system operation - and is not required for basic 100 MHz PCIe Gen5 operation with default settings.
What is the maximum allowable trace length for HCSL outputs without external termination?
The datasheet specifies performance validation with 5-inch microstrip traces. Due to the integrated 100Ω on-die termination, the PI6CB33801 supports direct connection to standard 100Ω differential PCB traces up to 5 inches without external resistors. Longer traces require impedance modeling and may need series damping or receiver-side termination depending on topology.
PI6CB33801ZLIEX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Fanout Buffer (Distribution)
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:8
- Differential - Input:Output:
- Yes/Yes
- Input:
- HCSL
- Output:
- HCSL
- Frequency - Max:
- 133.33 MHz
- Voltage - Supply:
- 3.135V ~ 3.465V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 48-TQFN (6x6)
PI6CB33801ZLIEX FAQ
1.How can I place an order for PI6CB33801ZLIEX through Aetrix?
Please submit a Request for Quotation (RFQ) for PI6CB33801ZLIEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PI6CB33801ZLIEX reliable?
The price and inventory of PI6CB33801ZLIEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6CB33801ZLIEX is usually 5 days.
3.What payment methods are accepted for PI6CB33801ZLIEX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6CB33801ZLIEX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PI6CB33801ZLIEX?
PI6CB33801ZLIEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PI6CB33801ZLIEX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PI6CB33801ZLIEX?
For technical support, including PI6CB33801ZLIEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6CB33801ZLIEX requirements.
6.How does Aetrix verify that PI6CB33801ZLIEX is sourced from the original manufacturer or authorized distributors?
All PI6CB33801ZLIEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6CB33801ZLIEX meets industry standards.
7.What is the process for return or replacement of PI6CB33801ZLIEX?
All PI6CB33801ZLIEX units undergo pre-shipment inspection (PSI). If there is an issue with PI6CB33801ZLIEX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PI6CB33801ZLIEX part is unused and in its original packaging.
Return procedure for PI6CB33801ZLIEX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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