Diodes Incorporated PI6CB33802ZLIEX-13R

Overview

PI6CB33802ZLIEX-13R from Diodes Incorporated is a very-low-power, 8-output PCIe clock buffer with integrated HCSL termination, supporting PCIe Gen1–Gen5 (100MHz), Ethernet (50/125/133.33MHz), differential cycle-to-cycle jitter <50ps, on-chip 85Ω termination per output, and individual OE# control for each of eight HCSL output pairs. It operates at 3.3V supply and targets high-density server, storage, and networking backplanes.

For engineers reviewing the PI6CB33802ZLIEX-13R datasheet, PI6CB33802ZLIEX-13R pinout, PI6CB33802ZLIEX-13R application, or PI6CB33802ZLIEX-13R equivalent, key selection criteria include PCIe Gen5-compliant phase jitter (<0.15ps RMS), programmable slew rate/amplitude per output, SMBus-configurable frequency modes, and tri-level strapping for address/bandwidth selection without external EEPROM.

Technical Context

The PI6CB33802 implements a proprietary low-jitter PLL architecture with selectable loop bandwidth (0.7–3.6 MHz) and optional bypass mode, enabling deterministic timing in PCIe root complex and switch fanout applications. Its input accepts HCSL differential signals at 50/100/125/133.33MHz, with spread-spectrum tolerance and automatic lock detection before output enable.

All eight HCSL outputs feature independent CMOS OE# pins and SMBus-controlled amplitude (0.6–0.85V) and slew rate (2.2–4.0 V/ns), while differential output-to-output skew remains ≤50ps. The device uses separate analog (VDDA/GNDA), digital (VDD_DIG/GND_DIG), and output (VDDO) power domains to isolate noise-sensitive PLL circuitry from switching outputs.

Key Specifications

Pinout & Package

Package: 48-lead 6mm × 6mm TQFN with exposed pad (EPAD) connected to GND. Pin pitch: 0.4mm. RoHS-compliant, halogen- and antimony-free "Green" construction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242A and Si53320-A01, the PI6CB33802ZLIEX-13R uniquely combines PCIe Gen5 jitter compliance, per-output hardware enable, and SMBus-programmable amplitude/slew rate-all within a 6×6mm TQFN package with integrated termination-making it optimal for high-density, thermally constrained server and storage designs requiring granular power management.

Availability

PI6CB33802ZLIEX-13R is available at Aetrix Electronics and suitable for PCIe Gen5 server backplanes, enterprise NVMe SSDs, 5G radio units, and high-density network switch line cards requiring stable component supply, long-term lifecycle assurance, and RoHS3-compliant sourcing.

Supply support for PI6CB33802ZLIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for industrial, computing, and communications markets.

The PI6CB33802 belongs to Diodes' PCIe-optimized clock buffer product line, designed specifically to meet Gen5 jitter, skew, and power requirements while simplifying layout through on-chip termination and flexible configuration.

FAQ

What is the function of the SADR_TRI and BW_SEL_TRI pins?

SADR_TRI selects one of three SMBus addresses (1101011b, 1101100b, or 1101101b) by applying low/mid/high voltage; BW_SEL_TRI configures PLL operating mode-low-bandwidth, bypass, or high-bandwidth-using tri-level latching. Both pins have internal pullup/pulldown resistors and require no external components for basic configuration.

Does the PI6CB33802ZLIEX-13R support spread-spectrum clocking (SSC)?

Yes-the device is explicitly spread-spectrum tolerant for PCIe applications (30–33 kHz triangular modulation) and non-PCIe use cases (up to 46 kHz). Its PLL design maintains lock and low additive jitter (<1ps) under SSC, ensuring reliable link training in Gen3–Gen5 systems.

How does the on-chip 85Ω termination affect PCB layout?

The integrated 85Ω termination eliminates the need for 32 external 85Ω resistors (16 per differential pair), reducing layer count, saving ~12 mm² per output pair, and removing stubs that degrade HCSL signal integrity. Layout requires only direct microstrip routing from Qn+/Qn− to connector/ASIC, with controlled 85Ω characteristic impedance.

Can the PI6CB33802ZLIEX-13R operate without SMBus configuration?

Yes-it boots into default 100MHz PCIe mode with all outputs enabled, 0.75V amplitude, and medium slew rate. Tri-level strapping pins set SMBus address and PLL mode at power-up; SMBus is optional for advanced tuning (e.g., 133.33MHz Ethernet, per-output amplitude adjustment, or low-power slew settings).