Diodes Incorporated PI6CBE33045ZHIEX-13R

Overview

PI6CBE33045ZHIEX-13R from Diodes Incorporated is a low-power, 4-output PCIe 6.0 and UPI-compliant zero-delay buffer (ZDB) / fanout clock buffer with integrated HCSL drivers, 85Ω on-chip termination, differential cycle-to-cycle jitter <50ps, and selectable PLL bandwidths (0.7–4 MHz). It operates from 3.3V supply and supports 1–400MHz input in fanout mode for high-speed server and AI accelerator timing distribution.

For engineers reviewing the PI6CBE33045ZHIEX-13R datasheet, PI6CBE33045ZHIEX-13R pinout, PI6CBE33045ZHIEX-13R application, or PI6CBE33045ZHIEX-13R equivalent, key selection criteria include PCIe 6.0 CC additive phase jitter (0.01 ps RMS), individual OE# control per output, SMBus-configurable ZDB/fanout mode, and 32-pin 5mm × 5mm TQFN (ZH) package compatibility with high-density PCB layouts.

Technical Context

The PI6CBE33045 implements a proprietary analog PLL architecture with tri-level configurable loop bandwidth (low/bypass/high) to optimize jitter performance across PCIe 6.0, QPI/UPI, and DB2000Q protocols. Its feedback path uses dedicated FBOUT_NC+/- pins for true zero-delay propagation matching, not external loopback.

It integrates four independent HCSL output pairs with on-die 85Ω termination, each controlled by active-low OE# pins (OE0#–OE3#), enabling dynamic power gating without affecting other outputs. SMBus interface (3.3V-tolerant, up to 500 kHz) allows runtime configuration of operating mode, address, and bandwidth - no external EEPROM required.

Key Specifications

Pinout & Package

Package: 32-pin, 5 mm × 5 mm TQFN (ZH) with exposed pad (EPAD) connected to ground - provides low thermal resistance and EMI shielding for high-frequency clock signals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock buffer applications.

Compared with IDT8T49N242A and Si53302-A01, the PI6CBE33045ZHIEX-13R uniquely delivers HCSL outputs with 85Ω on-die termination, PCIe 6.0 CC-validated 0.01 ps RMS additive jitter, and hardware-configurable ZDB/fanout modes - making it the only option that satisfies full PCIe 6.0, UPI, and DB2000Q timing stack requirements in a single 5mm × 5mm package.

Availability

PI6CBE33045ZHIEX-13R is available at Aetrix Electronics and suitable for PCIe 6.0 server platforms, AI accelerator interconnects, and high-density NVMe storage controllers requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant green packaging.

Supply support for PI6CBE33045ZHIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, communications, and industrial markets.

The PI6CBE33045 belongs to Diodes' PCIe-optimized clock buffer product line, engineered specifically to meet the sub-0.02 ps RMS additive jitter, skew, and power requirements of PCIe 6.0, UPI, and DB2000Q high-speed serial interconnects.

FAQ

What is the function of FBOUT_NC+ and FBOUT_NC- pins?

FBOUT_NC+ and FBOUT_NC- are internal feedback path outputs used exclusively for delay matching within the chip to achieve true zero-delay buffer operation. They must remain unconnected to external circuitry - any external loading will disrupt the internal delay calibration and degrade jitter performance or cause functional failure.

Can PI6CBE33045ZHIEX-13R operate without SMBus configuration?

Yes. The device defaults to fanout buffer mode with high-bandwidth PLL upon power-up, using tri-level latched inputs (SADR0_tri, BW_SEL_TRI) for address and bandwidth selection. SMBus is optional for dynamic reconfiguration; no firmware or host controller is required for basic operation.

How does the OE# pin behavior affect output state during power sequencing?

Each OE# pin is active-low with internal pulldown. When OE# = 1 (high), the corresponding Qn+/Qn- pair is disabled (outputs driven low); when OE# = 0 (low), outputs are enabled. During power-up, OE# remains low until configured, ensuring all outputs start enabled - critical for PCIe link training sequence timing.

Is PI6CBE33045ZHIEX-13R qualified for automotive applications?

No. This part is specified for industrial temperature range (–40°C to +85°C) and is not AEC-Q100 qualified. Diodes offers automotive-grade variants (e.g., PI6CBE33045QHIEX) with PPAP support, IATF 16949 manufacturing, and extended qualification testing - contact Diodes or Aetrix for those versions.