Diodes Incorporated PI6CBE33063ZLAIEX-13R

Overview

PI6CBE33063ZLAIEX-13R from Diodes Incorporated is a low-power, 6-output zero-delay buffer (ZDB) and fanout clock buffer optimized for PCIe 5.0/6.0 and UPI interfaces. It accepts a differential HCSL input (100 MHz nominal), delivers six matched HCSL outputs with on-chip 33 Ω termination, supports hardware/SMBus mode selection, and achieves PCIe 6.0-compliant additive phase jitter of 0.012 ps RMS in fanout mode. It is deployed in high-speed server motherboard clock distribution.

For engineers reviewing the PI6CBE33063ZLAIEX-13R datasheet, PI6CBE33063ZLAIEX-13R pinout, PI6CBE33063ZLAIEX-13R application, or PI6CBE33063ZLAIEX-13R equivalent, key selection criteria include differential output skew (<50 ps), selectable PLL bandwidth (0.7–4 MHz), individual OE# control per output, 3.3 V core supply, and compliance with PCIe 6.0 CC and DB2000Q jitter specifications.

Technical Context

The PI6CBE33063 implements a dual-mode architecture: in ZDB mode, it uses an internal feedback path (FBOUT_NC+/−) to achieve near-zero propagation delay; in fanout mode, it bypasses the PLL for direct signal distribution. Its proprietary PLL supports two configurable loop bandwidths (low: 0.7–1.4 MHz; high: 2–4 MHz) to optimize jitter suppression across PCIe and UPI protocols.

It integrates SMBus slave functionality (7-bit address 0x6C) for dynamic configuration of operating mode, output enables, and bandwidth selection. All six HCSL outputs feature independent CMOS OE# pins with internal pulldowns, enabling fine-grained power management without external logic.

Key Specifications

Pinout & Package

Package: 40-pin, 5 mm × 5 mm TQFN (ZLA) with exposed thermal pad (EPAD) connected to ground. RoHS-compliant, halogen- and antimony-free "Green" construction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock buffer applications.

Compared with IDT8T49N242A and Si53320-D-GM, the PI6CBE33063ZLAIEX-13R uniquely combines PCIe 6.0 CC jitter compliance, on-chip 33 Ω HCSL termination, tri-level bandwidth selection, and per-output OE#-making it the only drop-in solution for next-generation server clock trees requiring both ultra-low jitter and granular power control.

Availability

PI6CBE33063ZLAIEX-13R is available at Aetrix Electronics and suitable for PCIe 6.0 server motherboards, UPI-based CPU interconnects, and DB2000Q-compliant storage controllers requiring stable component supply, long-term lifecycle assurance, and full traceability.

Supply support for PI6CBE33063ZLAIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, communications, and industrial markets.

The PI6CBE33063 belongs to Diodes' PCIe-optimized clock buffer product line, engineered specifically to meet the stringent jitter, skew, and power requirements of PCIe 5.0/6.0 and UPI 11.4 GB/s interconnects in hyperscale data centers.

FAQ

What is the function of FBOUT_NC+ and FBOUT_NC− pins?

FBOUT_NC+ and FBOUT_NC− are internal differential feedback outputs used exclusively for delay path matching in zero-delay buffer (ZDB) mode. They must remain unconnected to external circuitry. Their sole purpose is to mirror the signal path delay of the main outputs, enabling precise cancellation of propagation delay - resulting in near-zero input-to-output latency.

Can PI6CBE33063ZLAIEX-13R operate without SMBus configuration?

Yes. The device defaults to fanout buffer mode at power-up with BW_SEL_TRI pulled high internally. All outputs are enabled unless OE# pins are asserted. SMBus is optional for dynamic reconfiguration of mode, bandwidth, or output states - hardware control via BW_SEL_TRI and OE# pins suffices for static deployments.

What is the maximum allowable input frequency in PLL bypass mode?

The maximum input frequency in PLL bypass mode is 400 MHz, as specified in the datasheet (fINBP parameter). This allows use beyond PCIe reference clocks - e.g., for 200 MHz UPI or 400 MHz custom high-speed interconnects - while maintaining <50 ps output skew and <0.1 ps additive jitter.

How does the BW_SEL_TRI pin determine PLL bandwidth?

BW_SEL_TRI is a tri-level input: logic 0 selects low-loop bandwidth (0.7–1.4 MHz), M (mid-voltage ≈ 1.65 V) bypasses the PLL, and logic 1 selects high-loop bandwidth (2–4 MHz). Internal pullup ensures default high state; no external resistors are required, simplifying layout and reducing BOM count.