Diodes Incorporated PI6CBE33065ZLAIEX-13R

Overview

PI6CBE33065ZLAIEX-13R from Diodes Incorporated is a low-power, 6-output PCIe 6.0 and UPI clock buffer supporting both zero-delay buffer (ZDB) and fanout modes. It delivers six differential HCSL outputs with on-chip 85Ω termination, <50ps output-to-output skew, and PCIe 6.0-compliant additive phase jitter of 0.012 ps RMS (CC architecture). It operates from a 3.3V supply and supports 1–400MHz input frequencies in bypass mode.

For engineers reviewing the PI6CBE33065ZLAIEX-13R datasheet, PI6CBE33065ZLAIEX-13R pinout, PI6CBE33065ZLAIEX-13R application, or PI6CBE33065ZLAIEX-13R equivalent, this device serves as a critical timing solution for high-speed serial interconnects requiring ultra-low jitter, individual output enable control, SMBus configurability, and dual-mode operation across PCIe Gen1–Gen6 and UPI/IF-UPI systems.

Technical Context

The PI6CBE33065 implements a proprietary PLL architecture with selectable bandwidth (0.7–4 MHz) to optimize jitter performance for PCIe Common Clock (CC) and SRIS topologies. Its ZDB mode uses internal feedback paths (FBOUT_NC±) to achieve near-zero propagation delay, while fanout mode bypasses the PLL for deterministic latency.

It integrates tri-level BW_SEL_TRI control for hardware-selectable PLL bandwidth or bypass, active-low OE# pins per output for granular power management, and SMBus interface for dynamic configuration of operating mode, output impedance, and spread-spectrum tolerance - all while maintaining HCSL compliance and 85Ω output impedance.

Key Specifications

Pinout & Package

Package: 40-pin, 5 mm × 5 mm TQFN (ZLA) with exposed pad (EPAD) connected to ground.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock buffer applications.

Compared with IDT8T49N242A and ICS843002AGI-01LFT, the PI6CBE33065ZLAIEX-13R uniquely combines PCIe 6.0 jitter compliance, dual ZDB/fanout operation, on-chip HCSL termination, and SMBus configurability - enabling single-part support for next-gen server, AI accelerator, and chiplet-based platforms without design compromises.

Availability

PI6CBE33065ZLAIEX-13R is available at Aetrix Electronics and suitable for PCIe 6.0 server motherboards, UPI-coupled CPU interconnects, and DB2000Q memory modules requiring stable component supply, long-term lifecycle assurance, and RoHS 3/Green compliance.

Supply support for PI6CBE33065ZLAIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for power management, signal integrity, and timing applications.

The PI6CBE33065 belongs to Diodes' high-performance clock buffer product line, engineered specifically for PCIe Gen6, UPI, and high-speed memory interconnects where ultra-low jitter, flexible topology support, and power-efficient operation are mandatory.

FAQ

What is the function of FBOUT_NC+ and FBOUT_NC− pins?

FBOUT_NC+ and FBOUT_NC− are internal feedback outputs used exclusively in Zero-Delay Buffer (ZDB) mode to match the signal path delay between input and output. They must remain unconnected to external circuitry - their sole purpose is internal delay compensation to achieve near-zero propagation delay, which is critical for PCIe Common Clock topology timing closure.

Can PI6CBE33065ZLAIEX-13R operate without SMBus configuration?

Yes. The device powers up in a default ZDB mode with low-bandwidth PLL enabled and all outputs active. SMBus is optional for runtime reconfiguration of operating mode (ZDB/fanout), PLL bandwidth, or output enable states. Hardware control via BW_SEL_TRI and OE# pins provides full functionality without SMBus initialization.

How does the BW_SEL_TRI pin determine PLL behavior?

BW_SEL_TRI is a tri-level input with internal pullup: logic 0 selects low-bandwidth PLL (1.1 MHz typ), M (mid-voltage ≈0.5×VDD) bypasses the PLL for fanout operation, and logic 1 selects high-bandwidth PLL (2.65 MHz typ). This hardware-selectable configuration allows jitter optimization per system architecture - low BW for PCIe CC, high BW for SRIS, bypass for deterministic latency.

Is the 85Ω output impedance configurable or fixed?

The 85Ω output impedance is fixed and implemented via on-chip termination - no external resistors or configuration registers are required. This value complies with Intel's HCSL v1.0 specification and is optimized for direct connection to 85Ω PCB traces used in PCIe 6.0 and UPI interfaces, eliminating layout complexity and signal integrity risks from external termination networks.