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Diodes Incorporated PI6CBE33083ZLIEX-13R
- Part No.:
- PI6CBE33083ZLIEX-13R
- Manufacturer:
- Diodes Incorporated
- Category:
- Clock Buffers, Drivers
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
PI6CBE33083ZLIEX-13R.pdf
- Description:
- CLOCK BUFFER V-QFN6060-48 T&R 3K
- Quantity:
- Payment:
- Shipping:
Inventory:4,031
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Product details
Overview
PI6CBE33083ZLIEX-13R from Diodes Incorporated is a low-power, 8-output PCIe 5.0/6.0 and UPI-compliant zero-delay buffer (ZDB) and fanout clock buffer. It accepts a differential HCSL input and delivers eight matched, on-chip-terminated (33Ω) HCSL outputs with <50ps output-to-output skew, supporting both 100MHz (default) and 133.33MHz operation in ZDB mode, and 1–400MHz in fanout mode - deployed in high-speed server backplanes and CPU interconnects.
For engineers reviewing the PI6CBE33083ZLIEX-13R datasheet, PI6CBE33083ZLIEX-13R pinout, PI6CBE33083ZLIEX-13R application, or PI6CBE33083ZLIEX-13R equivalent, this device is selected for PCIe 6.0 CC jitter compliance (0.01ps RMS), individual OE# control per output, SMBus/hardware mode selection, and dual-mode PLL architecture enabling precise timing synchronization in CPU-PCIe-UPI coherency domains.
Technical Context
The PI6CBE33083 implements a dual-loop PLL with selectable bandwidth (0.7–4 MHz) and bypass capability, enabling either ultra-low-jitter ZDB operation at 100/133.33MHz or wideband fanout buffering up to 400MHz. Its proprietary PLL achieves PCIe 6.0 Common Clock integrated phase jitter of 0.01ps RMS and DB2000Q additive jitter of 0.02ps RMS.
It integrates eight independent HCSL drivers with internal 33Ω termination, hardware-configurable frequency selection (100M_133M#), tri-level bandwidth control (BW_SEL_TRI), and SMBus-compatible control logic. Feedback pins (FBOUT_NC±) are unconnected externally and serve only internal delay-matching for true zero-delay propagation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count & Type | 8 differential HCSL outputs with integrated 33Ω on-die termination - eliminates external resistors and reduces board area. |
| ZDB Mode Frequencies | 100MHz (default) or 133.33MHz - selected via 100M_133M# pin; meets PCIe Gen3–Gen6 and UPI 11.4GB/s timing requirements. |
| Fanout Mode Range | 1–400MHz - supports flexible clock distribution across memory, I/O, and accelerator subsystems without PLL locking constraints. |
| Differential Skew | <50ps max output-to-output skew - ensures tight timing alignment across multi-lane PCIe/UPI interfaces. |
| PCIe 6.0 Phase Jitter | 0.01ps RMS (ZDB mode, Common Clock) - satisfies PCIe 6.0 CC jitter budget for error-free 64 GT/s signaling. |
| Additive Jitter (Fanout) | 0.012ps (PCIe 6.0 CC), 0.02ps (DB2000Q) - enables clean clock forwarding in retimer and switch applications. |
| Power Supply | 3.3V core (VDD/VDDA/VDDR) - compatible with standard server power rails; IDD = 100–115mA typical at 100MHz. |
| Package | 48-TQFN, 6×6mm (ZL suffix) - thermally enhanced, space-efficient footprint for dense CPU socket layouts. |
Pinout & Package
Package: 48-pin TQFN (6 mm × 6 mm, 0.5 mm pitch), exposed thermal pad (EPAD) connected to ground. Pin 1 marked by dot; pin numbering follows standard counter-clockwise convention from top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 PD# | CMOS Power-Down Control | Active-low global enable; internal pullup; asserts power-down state when low, exits on first high pulse after VDD stabilization. |
| 4 IN+, 5 IN- | Differential HCSL Input | Accepts 300–2900mVpp HCSL reference clock; common-mode range 150–900mV; supports single-ended drive with biasing. |
| 11,18,23,24,30,31,37,41 OE0#–OE7# | Per-Output Enable | Individual CMOS active-low controls; internal pulldowns; enables granular power gating of each HCSL pair. |
| 13/14 Q0+, Q0− … 39/40 Q7+, Q7− | Differential HCSL Outputs | Eight matched, 33Ω-terminated outputs; swing ±350mV typical; cross-point voltage 250–550mV. |
| 47 100M_133M# | Frequency Select Latch | Hardware-selectable ZDB mode: low = 133.33MHz, high (default) = 100MHz - sets PLL target frequency before lock. |
| 48 BW_SEL_TRI | Tri-Level Bandwidth Control | Low = 0.7–1.4MHz PLL BW, M = PLL bypass, High = 2.65–4MHz BW - adjusts jitter filtering vs. tracking response. |
| 6 SDATA, 7 SCLK | SMBus Interface | 3.3V-tolerant bidirectional data/clock; supports configuration of ZDB/fanout modes, output enables, and status reads. |
| 8 FBOUT_NC−, 9 FBOUT_NC+ | Internal Feedback Path | No external connection; provides matched delay path for zero-propagation-delay operation in ZDB mode. |
Key Features
| Feature | Design Value |
|---|---|
| Spread Spectrum Tolerance | Accepts 30–33kHz triangular SSC modulation - maintains lock and jitter performance under PCIe spread-spectrum clocking. |
| Individual Output Enable | Eight dedicated OE# pins (OE0#–OE7#) with internal pulldowns - enables dynamic power management per lane during link training or idle states. |
| Selectable PLL Bandwidth | Two configurable loop bandwidths (low/high) plus bypass mode - balances jitter attenuation vs. input clock tracking for varying source stability. |
| Differential Skew Control | <50ps max output-to-output skew across all eight HCSL pairs - ensures deterministic timing alignment for multi-lane PCIe 6.0 x16 and UPI 2x links. |
| On-Chip Termination | Integrated 33Ω series termination per HCSL output - eliminates 16 external resistors, reduces layout complexity, and improves signal integrity at 32GT/s. |
Applications
| PCIe 6.0 Server Root Complex | UPI 2.0 CPU-to-CPU Interconnect |
|---|---|
Use Scenario: Distributing synchronized 100MHz reference clocks across CPU die, PCH, and PCIe switch fabric in dual-socket Xeon/EPYC platforms. IC Role / Device Role / Timing Role: Zero-delay buffer providing phase-aligned, low-additive-jitter clocks to meet PCIe 6.0 Common Clock jitter spec (0.01ps RMS) and maintain BER <10⁻¹². Use Value: Enables simultaneous lock of all downstream receivers with sub-50ps skew, eliminating inter-lane deskew circuitry and reducing BOM cost. |
Use Scenario: Driving matched clock pairs between two CPUs in a cache-coherent UPI 2.0 topology operating at 133.33MHz and 11.4GB/s. IC Role / Device Role / Timing Role: ZDB-mode clock repeater delivering <0.15ps RMS phase jitter (IF-UPI) to meet Intel UPI 2.0 timing margin requirements. Use Value: Guarantees deterministic inter-CPU clock alignment for coherent snoop responses, reducing latency variation in NUMA memory access. |
| PCIe Retimer Fanout Distribution | DB2000Q Compliant Switch Fabric |
Use Scenario: Buffering and fanning out 100MHz PCIe reference clocks to multiple retimers in AI accelerator racks with mixed Gen4/Gen5/Gen6 devices. IC Role / Device Role / Timing Role: Fanout buffer mode (PLL bypass) delivering 0.012ps additive jitter - preserves source clock integrity while scaling to 8 endpoints. Use Value: Eliminates cascaded jitter accumulation across retimer stages, maintaining eye opening at 64 GT/s over long backplane traces. |
Use Scenario: Providing low-jitter clocking to DB2000Q-compliant switches in CXL 3.0 memory expansion systems requiring 0.02ps additive jitter compliance. IC Role / Device Role / Timing Role: Fanout buffer with 0.02ps DB2000Q additive jitter - satisfies stringent jitter floor for 32GT/s serial link convergence. Use Value: Supports deterministic link training and stable 256-byte payload transmission without retransmission due to timing violations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PCIe clock buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT8T49N242A | 8-output LVDS/LVPECL buffer; no integrated HCSL termination; requires external 50Ω resistors; higher IDD (180mA). | Targets legacy LVDS-based infrastructure; lacks PCIe 6.0 CC jitter compliance (0.028ps typ) and SMBus configurability. | Choose only if system uses LVDS receivers or requires programmable output voltage (1.5–3.3V). |
| Si53320-B-GM | 8-output HCSL buffer with integrated termination; fixed 100MHz ZDB mode only; no 133.33MHz support or tri-level BW control. | Limited to PCIe Gen3–Gen5 root complex; cannot support UPI 2.0 133.33MHz or DB2000Q 0.02ps requirement. | Select when UPI/PCIe 6.0 coexistence is not required and design prioritizes pin-count reduction over flexibility. |
Compared with IDT8T49N242A and Si53320-B-GM, the PI6CBE33083ZLIEX-13R uniquely combines PCIe 6.0 CC jitter (0.01ps), dual-frequency ZDB (100/133.33MHz), and per-output OE# control - making it the only option qualified for next-gen dual-socket servers requiring UPI 2.0 + PCIe 6.0 co-timing.
Availability
PI6CBE33083ZLIEX-13R is available at Aetrix Electronics and suitable for PCIe 6.0 server motherboards, UPI 2.0 CPU interconnects, and DB2000Q switch fabrics requiring stable component supply, long-term lifecycle assurance, and traceable green sourcing.
Supply support for PI6CBE33083ZLIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for high-reliability industrial, computing, and communications applications.
The PI6CBE33083 belongs to Diodes' Precision Timing product line, engineered specifically for PCIe Gen5/Gen6, UPI, and CXL clock distribution - emphasizing ultra-low jitter, hardware/SMBus configurability, and robust signal integrity in high-speed compute platforms.
FAQ
What is the function of FBOUT_NC± pins?
FBOUT_NC− (Pin 8) and FBOUT_NC+ (Pin 9) are internal feedback terminals used exclusively for delay-path matching within the chip to achieve true zero-propagation-delay operation in ZDB mode. They must remain unconnected to any external circuitry - floating or grounded connections will disrupt ZDB functionality and increase skew.
Can PI6CBE33083ZLIEX-13R operate without SMBus configuration?
Yes - all critical functions (ZDB/fanout mode, frequency selection, output enables) are controllable via hardware pins (100M_133M#, BW_SEL_TRI, OE0#–OE7#). SMBus is optional and used only for advanced diagnostics, status monitoring, or dynamic reconfiguration during runtime; default pin-strapped behavior fully supports boot-time clock distribution.
How does the device handle spread-spectrum clocking (SSC)?
The PI6CBE33083 is explicitly designed to tolerate 30–33kHz triangular SSC modulation on its IN+/IN− inputs. Its PLL architecture maintains lock and preserves jitter performance under SSC, meeting PCIe 6.0 spread-spectrum compliance without requiring external SSC stripping or filtering circuits.
What is the minimum input clock slew rate supported?
The device requires a minimum differential input slew rate of 0.4 V/ns (measured across ±75mV window around differential zero), verified per DS45453 Rev 3-2. This ensures reliable edge detection and jitter-free PLL locking - typical HCSL sources (e.g., PCIe root complex clocks) exceed this requirement by >5×.
PI6CBE33083ZLIEX-13R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Clock Buffer
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:8
- Differential - Input:Output:
- Yes/Yes
- Input:
- HCSL
- Output:
- HCSL
- Frequency - Max:
- 400 MHz
- Voltage - Supply:
- 3.135V ~ 3.465V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 48-TQFN (6x6)
PI6CBE33083ZLIEX-13R FAQ
1.How can I place an order for PI6CBE33083ZLIEX-13R through Aetrix?
Please submit a Request for Quotation (RFQ) for PI6CBE33083ZLIEX-13R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PI6CBE33083ZLIEX-13R reliable?
The price and inventory of PI6CBE33083ZLIEX-13R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6CBE33083ZLIEX-13R is usually 5 days.
3.What payment methods are accepted for PI6CBE33083ZLIEX-13R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6CBE33083ZLIEX-13R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PI6CBE33083ZLIEX-13R?
PI6CBE33083ZLIEX-13R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PI6CBE33083ZLIEX-13R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PI6CBE33083ZLIEX-13R?
For technical support, including PI6CBE33083ZLIEX-13R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6CBE33083ZLIEX-13R requirements.
6.How does Aetrix verify that PI6CBE33083ZLIEX-13R is sourced from the original manufacturer or authorized distributors?
All PI6CBE33083ZLIEX-13R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6CBE33083ZLIEX-13R meets industry standards.
7.What is the process for return or replacement of PI6CBE33083ZLIEX-13R?
All PI6CBE33083ZLIEX-13R units undergo pre-shipment inspection (PSI). If there is an issue with PI6CBE33083ZLIEX-13R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PI6CBE33083ZLIEX-13R part is unused and in its original packaging.
Return procedure for PI6CBE33083ZLIEX-13R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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