Diodes Incorporated PI6CBE33085ZLIEX-13R

Overview

PI6CBE33085ZLIEX-13R from Diodes Incorporated is a low-power, 8-output PCIe 6.0 and UPI clock buffer with integrated PLL, supporting both zero-delay buffer (ZDB) and fanout modes. It delivers eight differential HCSL outputs at 100MHz or 133.33MHz, features on-chip 85Ω termination, <50ps output-to-output skew, and meets PCIe 6.0 CC additive phase jitter ≤0.012 ps RMS in fanout mode. It is deployed in high-speed server motherboard clock distribution.

For engineers reviewing the PI6CBE33085ZLIEX-13R datasheet, PI6CBE33085ZLIEX-13R pinout, PI6CBE33085ZLIEX-13R application, or PI6CBE33085ZLIEX-13R equivalent, key selection criteria include PCIe 6.0/UP11.4GB/s jitter compliance, individual OE# control per output, SMBus-configurable ZDB/fanout mode, and 3.3V core supply with power-down capability.

Technical Context

The PI6CBE33085 implements a proprietary low-jitter PLL architecture with selectable bandwidth (0.7–4 MHz) and hardware/SMBus-controlled mode switching between ZDB and fanout operation. Its dual-mode design enables precise timing alignment for PCIe root complex and switch applications while maintaining sub-50ps cycle-to-cycle jitter.

It supports differential HCSL inputs (IN+/IN−) and outputs (Q0+ to Q7−), with dedicated feedback pins (FBOUT_NC+/−) enabling true zero-delay propagation in ZDB mode. The device integrates internal pullup/pulldown resistors on control pins (PD#, BW_SEL_TRI, 100M_133M#) and provides tri-level logic support for bandwidth selection.

Key Specifications

Pinout & Package

Package: 48-pin TQFN, 6×6 mm, exposed pad (ZL suffix), RoHS-compliant and halogen-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock buffer applications.

Compared with IDT8T49N242A and Si53320-D-GM, the PI6CBE33085ZLIEX-13R uniquely balances PCIe 6.0–certified jitter performance, per-output power control, and cost-effective integration-making it optimal for high-volume server clock trees where ZDB/fanout duality and 85Ω HCSL termination are essential.

Availability

PI6CBE33085ZLIEX-13R is available at Aetrix Electronics and suitable for PCIe 6.0 server motherboards, UPI-based multi-socket CPUs, and DB2000Q-compliant DDR5 memory subsystems requiring stable component supply and long-term lifecycle support.

Supply support for PI6CBE33085ZLIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for power management, signal integrity, and connectivity applications.

The PI6CBE33085 belongs to Diodes' high-performance clock buffer product line, designed specifically for PCIe 6.0, UPI, and DB2000Q timing-critical infrastructure in data center and AI acceleration platforms.

FAQ

What is the function of FBOUT_NC+ and FBOUT_NC− pins?

FBOUT_NC+ and FBOUT_NC− are internal feedback terminals used exclusively for delay path matching within the chip to achieve true zero-propagation-delay operation in ZDB mode. They must remain unconnected to external circuitry; any external loading will disrupt ZDB functionality and increase jitter.

Can PI6CBE33085ZLIEX-13R operate in both ZDB and fanout modes simultaneously?

No. The device operates exclusively in one mode at a time-either ZDB (100/133.33MHz) or fanout (1–400MHz)-selected by the latched state of BW_SEL_TRI and 100M_133M# pins at power-up or PD# deassertion. Mode switching requires a full reset cycle via PD# toggling.

Does PI6CBE33085ZLIEX-13R require external termination resistors for HCSL outputs?

No. The device integrates 85Ω on-chip termination for all eight HCSL outputs, eliminating the need for external 85Ω resistors. This reduces PCB layout complexity, saves board space, and improves impedance matching consistency across all outputs.

How does the BW_SEL_TRI pin affect PLL performance?

BW_SEL_TRI is a tri-level latched input that selects PLL bandwidth: logic 0 enables low-bandwidth mode (0.7–1.4 MHz), M enables PLL bypass (no PLL), and logic 1 enables high-bandwidth mode (2–4 MHz). Bandwidth selection directly impacts jitter peaking, lock time, and sensitivity to input jitter-critical for PCIe 6.0 vs. UPI optimization.