Diodes Incorporated PI6CBE33123ZDIEX-13R

Overview

PI6CBE33123ZDIEX-13R from Diodes Incorporated is a low-power, 12-output PCIe 5.0/6.0 and UPI clock buffer with integrated PLL, supporting both zero-delay buffer (ZDB) and fanout modes. It delivers 100MHz or 133.33MHz differential HCSL outputs with on-chip 33Ω termination, <50ps output-to-output skew, and PCIe 6.0-compliant additive phase jitter of 0.012ps RMS in fanout mode - deployed in high-speed server backplanes and CPU interconnects.

For engineers reviewing the PI6CBE33123ZDIEX-13R datasheet, PI6CBE33123ZDIEX-13R pinout, PI6CBE33123ZDIEX-13R application, or PI6CBE33123ZDIEX-13R equivalent, key selection criteria include differential HCSL output impedance matching, SMBus-addressable configuration for multi-device systems, PLL bandwidth selection for jitter optimization, and power-down sequencing via PD# with sub-1.1mA IDD_PD current.

Technical Context

The PI6CBE33123 implements a proprietary analog PLL architecture with selectable low-bandwidth (1.1MHz) or high-bandwidth (2.65MHz) loop filters to suppress reference clock jitter while maintaining PCIe 6.0 CC compliance. Its dual-mode operation is hardware-latched via BW_SEL_TRI and 100M_133M# pins, enabling deterministic ZDB (zero propagation delay via internal feedback path) or fanout (buffered pass-through) behavior without firmware intervention.

All 12 HCSL outputs feature individual OE# control, on-die 33Ω source termination, and matched trace routing support via dedicated FBOUT_NC± pins - which are internally connected and must remain unconnected externally to preserve delay-matching integrity for ZDB timing accuracy.

Key Specifications

Pinout & Package

PI6CBE33123ZDIEX-13R uses a 64-lead, 9mm × 9mm TQFN package (ZD suffix), thermally enhanced with exposed EPAD tied to ground. Pin layout follows standard QFN symmetry with dedicated power domains (VDDA, VDDR, VDDO), isolated analog/digital grounds (GNDA, GNDR, GND), and strict separation between input, feedback, and output differential pairs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock buffer applications.

Compared with IDT8T49N242B and Si53320-B-GM, the PI6CBE33123ZDIEX-13R uniquely combines PCIe 6.0-compliant jitter, hardware-selectable ZDB/fanout modes, 12 individually controllable outputs, and 9 SMBus addresses - making it the only solution that satisfies next-gen server clock tree requirements for scalability, low jitter, and deterministic startup without firmware dependency.

Availability

PI6CBE33123ZDIEX-13R is available at Aetrix Electronics and suitable for PCIe 6.0 server backplanes, CPU-UPI interconnects, and AI accelerator rack clock trees requiring stable component supply, long-term lifecycle assurance, and RoHS 3-compliant packaging.

Supply support for PI6CBE33123ZDIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for power management, signal integrity, and timing applications - with manufacturing certified to IATF 16949 and product lines compliant with RoHS 3, Halogen-Free, and AEC-Q standards.

The PI6CBE33123 belongs to Diodes' high-performance clock buffer product line, engineered specifically for PCIe 5.0/6.0, UPI, and CXL interconnects where ultra-low additive jitter, deterministic ZDB timing, and scalable multi-device configuration are mandatory.

FAQ

What is the function of FBOUT_NC+ and FBOUT_NC- pins?

FBOUT_NC+ and FBOUT_NC- are internal differential feedback outputs used exclusively for delay path matching in zero-delay buffer (ZDB) mode. They must remain unconnected to any external circuitry. Their sole purpose is to replicate the signal path delay of the main outputs, ensuring precise phase alignment and true zero net propagation delay - critical for UPI and PCIe ZDB timing compliance.

Can PI6CBE33123ZDIEX-13R operate without SMBus configuration?

Yes. All critical functions - including ZDB/fanout mode, output frequency (100MHz/133.33MHz), PLL bandwidth, and SMBus address - are latched at power-up via hardware pins (BW_SEL_TRI, 100M_133M#, SADR0_TRI/SADR1_TRI). SMBus is optional and used only for dynamic runtime reconfiguration, such as changing output enables or PLL settings after system boot.

How does the device achieve PCIe 6.0 jitter compliance?

The PI6CBE33123 achieves PCIe 6.0 additive phase jitter compliance (0.01ps RMS in ZDB mode, 0.012ps RMS in fanout mode) through its proprietary analog PLL with selectable loop bandwidths, differential HCSL output stage with matched slew rates (<20% mismatch), and on-chip 33Ω termination that eliminates external resistor-induced jitter sources. Measurement data is validated per PCI-SIG test methodology using 100k-cycle RMS integration.

Is the 64-pin TQFN package thermally adequate for full-load operation?

Yes. The 9mm × 9mm TQFN package features an exposed EPAD thermally connected to PCB ground plane, enabling a junction-to-ambient thermal resistance (θ_JA) of ≤35°C/W under standard 2oz copper, 4-layer board conditions. At full load (55mA, 100MHz), junction temperature remains below 85°C ambient + (55mA × 3.3V × 35°C/W) ≈ 92°C - well within the 125°C absolute maximum rating and industrial-grade operating range.