Diodes Incorporated PI6CBE33125ZDIEX

Overview

PI6CBE33125 from Diodes Incorporated is a low-power, 12-output PCIe 6.0 and UPI clock buffer supporting both zero-delay buffer (ZDB) and fanout modes. It delivers twelve differential HCSL outputs with on-chip 85Ω termination, operates at 100MHz or 133.33MHz in ZDB mode, and achieves PCIe 6.0-compliant additive phase jitter of 0.012 ps RMS in fanout mode - deployed in high-speed server backplanes and CPU interconnects.

For engineers reviewing the PI6CBE33125 datasheet, PI6CBE33125 pinout, PI6CBE33125 application, or PI6CBE33125 equivalent, key selection criteria include differential output skew <50ps, hardware/SMBus-selectable PLL bandwidths, individual OE# per output, spread-spectrum tolerance, and support for PCIe 6.0 CC and DB2000Q jitter specifications.

Technical Context

The PI6CBE33125 integrates a proprietary low-jitter PLL with selectable bandwidth (0.7–4 MHz) and bypass capability, enabling precise timing alignment in both common-clocked and SRIS architectures. Its dual-mode operation is controlled via tri-level latches (BW_SEL_TRI, 100M_133M#) and SMBus commands, allowing dynamic reconfiguration without reset.

It features twelve matched HCSL outputs with internal 85Ω termination, differential input pair (IN+/IN−), and dedicated feedback pins (FBOUT_NC+/−) for true zero-delay propagation. All outputs support independent enable/disable via active-low OE# pins, and SMBus interface provides up to nine address options with tri-level SADR0_TRI/SADR1_TRI configuration.

Key Specifications

Pinout & Package

Package: 64-lead, 9mm × 9mm TQFN (ZD) with exposed pad (EPAD) connected to ground. RoHS-compliant, halogen- and antimony-free "Green" construction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock buffer applications.

Compared with IDT8T49N242A and Si53320-B-GM, the PI6CBE33125 uniquely combines ZDB/fanout dual-mode operation, per-output enable, and PCIe 6.0-compliant jitter in a single 9×9mm package - making it optimal for next-gen server and AI platform clock trees where timing margin and power efficiency are co-constrained.

Availability

PI6CBE33125 is available at Aetrix Electronics and suitable for PCIe 6.0 server backplanes, multi-socket CPU interconnects, and AI accelerator rack clock trees requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant green packaging.

Supply support for PI6CBE33125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs, with emphasis on power management, signal integrity, and timing solutions for industrial, computing, and communications markets.

The PI6CBE33125 belongs to Diodes' high-performance clock buffer product line, engineered specifically for PCIe 6.0, UPI, and CXL timing ecosystems - prioritizing ultra-low jitter, dual-mode flexibility, and system-level power optimization.

FAQ

What is the function of FBOUT_NC+ and FBOUT_NC− pins?

FBOUT_NC+ and FBOUT_NC− are internal feedback terminals used exclusively for delay path matching in zero-delay buffer (ZDB) mode. They must remain unconnected to external circuitry. Their sole purpose is to replicate the signal path delay from input to output, enabling true zero-propagation-delay operation - confirmed in the datasheet's Pin Description table and Block Diagram.

Can PI6CBE33125 operate in fanout mode at 133.33MHz?

No - fanout mode supports 1–400MHz, but the 133.33MHz frequency is only valid in ZDB mode, as specified in the Frequency Select Table. In fanout mode, the device locks to the input frequency; the 133.33MHz option is enabled solely via the 100M_133M# pin in ZDB configuration, per DS43626 Rev 4-2 Section 5.

How does SMBus address selection work with SADR0_TRI and SADR1_TRI?

SADR0_TRI and SADR1_TRI are tri-level inputs (0/M/1) sampled at first PD# deassertion to set one of nine SMBus addresses (D8h–CEh), as defined in the SMBus Address Selection Table. Each pin has internal pulldown; logic '0' = grounded, '1' = VDD, 'M' = mid-voltage (0.5×VDD). No external pull-up/down resistors are required.

Is PI6CBE33125 qualified for automotive applications?

The PI6CBE33125 is not AEC-Q100 qualified. Diodes Incorporated explicitly states that automotive-grade variants require specific change control, PPAP capability, and IATF 16949 manufacturing - and directs users to contact their representative for such versions. This part is rated for industrial temperature (–40°C to +85°C) only.