Diodes Incorporated PI6CDBL401BZHIE

Overview

PI6CDBL401BZHIE from Diodes Incorporated is a 4-output, low-power PCIe Gen1/Gen2/Gen3 clock buffer with integrated 100Ω output terminations, HCSL/LVDS-compatible differential outputs, programmable slew rate (1–4.5 V/ns), and 3.3V core / 1.8–3.3V output supply support. It operates across -40°C to +85°C and delivers <50 ps cycle-to-cycle jitter in PLL mode at 100MHz for high-reliability server and storage interconnects.

For engineers reviewing the PI6CDBL401BZHIE datasheet, PI6CDBL401BZHIE pinout, PI6CDBL401BZHIE application, or PI6CDBL401BZHIE equivalent, this device supports SMBus-configurable output enables, tri-level PLL mode selection (HiBW/Bypass/LoBW), PCIe-compliant phase jitter (≤1 ps rms for Gen3), and industrial-temperature operation - critical for PCIe slot expansion, NVMe controller timing, and multi-lane switch fabric synchronization.

Technical Context

The PI6CDBL401BZHIE integrates a low-jitter PLL with selectable bandwidth (HiBW/LoBW) or bypass mode, enabling precise clock distribution while maintaining PCIe Gen3 additive phase jitter ≤0.05 ps rms. Its differential inputs accept 100MHz reference clocks with 300–1450 mVpp swing and 0.4 V/ns minimum slew rate.

All four HCSL outputs feature independent OE# pins, programmable amplitude (0.6–0.9V), and matched skew ≤50 ps between outputs. The device uses separate analog (VDDA3.3/VDDR3.3), digital (VDDDIG3.3), and output (VDDO1.8) power domains to isolate noise-sensitive PLL and clock paths.

Key Specifications

Pinout & Package

PI6CDBL401BZHIE is housed in a 32-pin Thin Quad Flat No-Lead (TQFN) package with 5×5 mm body and 0.5 mm pitch (package code ZH32). The exposed thermal pad enhances thermal dissipation (θJA = 44.7°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242A and ICS843002AG-01, the PI6CDBL401BZHIE uniquely balances PCIe Gen3 compliance, per-output configurability, and TQFN space efficiency - making it optimal for mid-channel-count, thermally constrained, and firmware-tunable PCIe timing architectures.

Availability

PI6CDBL401BZHIE is available at Aetrix Electronics and suitable for PCIe slot expansion, NVMe controller timing, and enterprise storage backplane applications requiring stable component supply, long-term lifecycle support, and industrial-temperature qualification.

Supply support for PI6CDBL401BZHIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for power management, signal integrity, and connectivity applications.

The PI6CDBL401BZHIE belongs to Diodes' Pericom timing product line, designed specifically for high-speed serial interface clock distribution in PCIe, SATA, and SGMII systems - emphasizing low jitter, flexible voltage operation, and robust industrial reliability.

FAQ

What is the function of the FB_DNC and FB_DNC# pins?

FB_DNC and FB_DNC# are internally connected differential feedback pins used exclusively by the on-chip PLL. They must remain unconnected in all designs - no external components or routing is permitted. These pins are not user-accessible and serve only for internal loop stabilization.

Can PI6CDBL401BZHIE drive LVDS receivers directly?

Yes - the PI6CDBL401BZHIE's HCSL outputs can drive LVDS inputs using recommended external biasing networks (e.g., 140Ω termination resistors and 1.2V common-mode bias). The datasheet provides validated LVDS load configurations, including R7a/R7b and R8a/R8b resistor values for 1.2V Vcm compliance.

How does CKPWRGD_PD# interact with OE# pin behavior?

CKPWRGD_PD# controls global power-up sequencing: a rising edge initiates PLL lock and enables outputs if OE# pins are low. When CKPWRGD_PD# is low, all outputs are forced into high-impedance regardless of OE# state. OE# pins only affect output enable status when CKPWRGD_PD# is high and the device is powered.

What SMBus address options are supported, and how are they selected?

The PI6CDBL401BZHIE supports three SMBus addresses (0x6B, 0x6C, 0x6D) selected via the tri-level SADR_tri pin. During first application of CKPWRGD_PD#, the pin voltage level (low/mid/high) latches the address. This enables up to three identical buffers on a single SMBus without address conflict.