Diodes Incorporated PI6CDBL402BLIE

Overview

PI6CDBL402BLIE from Pericom Semiconductor is a PCIe 3.0-compliant, low-noise, 4-output differential clock buffer with integrated PLL/bypass mode selection, designed as a companion to PCIe 3.0 clock generators. It distributes SRC differential clock inputs to four HCSL output pairs (OUT0–OUT3), supports 1.8V–3.3V independent output supply, delivers <60 ps output-to-output skew, and operates across 1–400 MHz in bypass mode or at 100 MHz in PLL mode - deployed in high-speed server motherboard clock trees.

For engineers reviewing the PI6CDBL402BLIE datasheet, PI6CDBL402BLIE pinout, PI6CDBL402BLIE application, or PI6CDBL402BLIE equivalent, key selection criteria include additive RMS phase jitter (<1 ps for PCIe Gen 3), programmable PLL bandwidth, SMBus-configurable output enable per channel, and dual-mode operation (PLL/Bypass) with independent VDDO rail support.

Technical Context

The PI6CDBL402BLIE implements a dual-path architecture: a low-jitter PLL path (100 MHz fixed output) and a direct bypass path (1–400 MHz), both feeding four differential HCSL outputs. Input clock conditioning includes phase jitter filtering optimized for PCIe Gen 1/2/3 compliance, with additive RMS phase jitter as low as 0.05 ps (Gen 3, bypass mode).

Control is implemented via 3.3V LVTTL pins (PLL/BYPASS#, PWRDWN#, OE_0/OE_3, OE_INV) and an SMBus slave interface (7-bit address 0x6E) supporting indexed block read/write for register-level output enable, PLL bandwidth selection (high/low), and power-down mode configuration - all while maintaining <300 µs power-down assertion latency.

Key Specifications

Pinout & Package

Package: 28-pin TSSOP (L28), 173-mil wide, Pb-free and Green (per ordering code suffix 'E'). Dimensions: 9.6 × 4.3 × 1.2 mm (L × W × H), 0.65 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT 8P34S1208NLGI and ON Semi NB3N551DR2G, the PI6CDBL402BLIE uniquely combines PCIe Gen 3 jitter compliance, per-output enable, VDDO voltage flexibility, and SMBus configurability - making it optimal for next-generation server platforms requiring adaptive clock management and mixed-voltage interoperability.

Availability

PI6CDBL402BLIE is available at Aetrix Electronics and suitable for server motherboard design, PCIe switch fanout, and embedded GPU compute node development requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for PI6CDBL402BLIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, interface, and signal-integrity solutions for datacenter, communications, and computing markets.

The PI6CDBL402BLIE belongs to Pericom's PCIe clock buffer product line, engineered specifically to meet stringent Gen 3 jitter and skew requirements while enabling flexible system-level clock tree partitioning and power management.

FAQ

What is the minimum input clock frequency supported in bypass mode?

The PI6CDBL402BLIE supports bypass mode operation from 1 MHz to 400 MHz. At 1 MHz, output duty cycle distortion remains within ±1.3%, and jitter performance meets PCIe Gen 1 specifications. Input slew rate must exceed 0.4 V/ns, and common-mode voltage must stay between 300 mV and 725 mV for reliable detection.

Can OE_0 and OE_3 be used simultaneously to gate different output pairs?

Yes - OE_0 directly controls OUT0/OUT0#, and OE_3 directly controls OUT3/OUT3#. OUT1/OUT1# and OUT2/OUT2# are enabled/disabled together via SMBus register bits (Byte 1, Bits 1/2 and 5/6). This allows independent gating of output Pair 0 and Pair 3 while synchronizing Pairs 1 and 2 through software control.

Does the device require external termination for HCSL outputs?

No external termination is required. The PI6CDBL402BLIE drives standard HCSL loads (typically 50 Ω to VDDO/2) using internal 17 mA current sources. When driving LVDS receivers, external 140 Ω or 75 Ω Thevenin termination is recommended per the application note - but this is receiver-side adaptation, not device termination.

How does PLL bandwidth selection affect phase jitter performance?

Setting PLL_BW# low selects high bandwidth (≈10 MHz), improving transient response but increasing sensitivity to input jitter. Setting it high selects low bandwidth (≈2–4 MHz), enhancing jitter filtering - especially critical for PCIe Gen 3, where measured additive RMS phase jitter drops to 0.05 ps in low-BW bypass mode and 0.5 ps in PLL mode.