Diodes Incorporated PI6CDBL402BLIEX

Overview

PI6CDBL402BLIEX from Pericom Semiconductor is a PCIe 3.0-compliant, low-noise, 4-output differential clock buffer with selectable PLL/bypass operation, 1.8–3.3V output supply flexibility, <60ps output-to-output skew, and <1 ps additive RMS phase jitter in PCIe Gen 3 mode. It serves as a companion to PCIe clock generators (e.g., PI6C410) in high-speed server and storage motherboard clock distribution.

For engineers reviewing the PI6CDBL402BLIEX datasheet, PI6CDBL402BLIEX pinout, PI6CDBL402BLIEX application, or PI6CDBL402BLIEX equivalent, key selection criteria include PCIe Gen 1/2/3 backward compatibility, SMBus programmable PLL bandwidth, independent VDDO per output bank, low-power HCSL output drive, and 28-pin TSSOP packaging for space-constrained PCB layouts.

Technical Context

The PI6CDBL402BLIEX implements a dual-mode architecture: PLL mode locks to a 100 MHz reference for jitter cleanup and frequency translation, while bypass mode supports 1–400 MHz input frequencies with minimal additive jitter (<25 ps cycle-to-cycle). Its differential SRC/SRC# inputs accept 0.7V HCSL-compatible signals with 300–1450 mV p-p swing and 0.4 V/ns minimum slew rate.

Output control integrates hardware pins (OE_0/OE_3, PWRDWN#, OE_INV) and SMBus register access (7-bit slave address 0x6E), enabling dynamic output enable/disable, PLL bandwidth selection (high/low), and power-down sequencing with <300 µs activation delay and <1 ms stabilization time after de-assertion.

Key Specifications

Pinout & Package

Package: 28-pin Pb-free Green TSSOP (L28), 173-mil wide, JEDEC MO-153F/AE compliant, 0.65 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT 8T49N241 and Microchip SY89467L, the PI6CDBL402BLIEX uniquely balances PCIe Gen 3 jitter performance, multi-voltage output flexibility, and SMBus configurability-making it optimal for scalable, power-aware server and storage platforms requiring precise clock domain isolation.

Availability

PI6CDBL402BLIEX is available at Aetrix Electronics and suitable for server motherboard design, enterprise SSD timing, high-density storage enclosures, and PCIe switch-based accelerator cards requiring stable component supply across extended product lifecycles.

Supply support for PI6CDBL402BLIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, interface, and signal-integrity solutions for datacenter and communications infrastructure.

The PI6CDBL402BLIEX belongs to Pericom's PCIe Gen 3 clock buffer product line, engineered specifically for low-additive-jitter fan-out in multi-lane, mixed-voltage PCIe 3.0 systems with stringent thermal and layout constraints.

FAQ

What is the default power-up state of the PI6CDBL402BLIEX outputs?

At power-up, all outputs are disabled (LOW/LOW differential state) until PWRDWN# is de-asserted and OE bits are set via SMBus or hardware pins. The device enters bypass mode by default (PLL/BYPASS# = high), and output enables require explicit activation-either through OE_0/OE_3 pins or SMBus register Byte0 Bit1/2/5/6. This prevents spurious clocking during boot sequence.

Can the PI6CDBL402BLIEX drive both 1.8V and 3.3V loads simultaneously?

Yes. The device has four independent VDDO pins (Pins 5, 11, 18, 24), each powering one output pair (OUT0, OUT1, OUT2, OUT3). Each VDDO can be set to 1.8 V, 2.5 V, or 3.3 V, allowing concurrent generation of 0.7V HCSL clocks at different voltage levels-e.g., OUT0/OUT0# at 1.8V for an SSD controller and OUT2/OUT2# at 3.3V for a PCIe PHY-without external level shifters.

How does the SMBus address work, and what happens during PWRDWN# assertion?

The PI6CDBL402BLIEX uses a fixed 7-bit SMBus slave address of 0x6E (1101110b). During PWRDWN# assertion, all SMBus registers become inaccessible-no reads or writes are possible until PWRDWN# is de-asserted and the device completes its 1 ms stabilization period. Register access resumes only after tSTAB (≤1 ms) elapses and the internal clock is stable.

What is the significance of the "additive jitter" specification, and how is it measured?

Additive jitter quantifies noise introduced solely by the buffer-not inherited from the input clock-and is calculated as √(total_jitter² − input_jitter²). For PI6CDBL402BLIEX, this value is ≤0.05 ps RMS in PCIe Gen 3 bypass mode (10 kHz–50 MHz), verified using a calibrated 9FG432AKLF source. This metric directly impacts bit-error rate in high-speed serial links and is critical for PCIe Gen 3 compliance validation.