Diodes Incorporated PI6CEQ20200LE

Overview

PI6CEQ20200LE from Pericom Semiconductor is a PCIe Gen2/Gen3-compliant zero-delay clock buffer with integrated equalization, dual HCSL outputs, 40ps typ cycle-to-cycle jitter, and 3.3V operation in TSSOP-20 package. It serves as a high-integrity clock distribution device for PCIe root complexes and switches where long-trace input signal degradation must be compensated.

For engineers reviewing the PI6CEQ20200LE datasheet, PI6CEQ20200LE pinout, PI6CEQ20200LE application, or PI6CEQ20200LE equivalent, key selection criteria include HCSL output compliance, PLL bandwidth selectability (0.25–3 MHz), sub-10ps output skew, Gen3 jitter performance (0.61–1.0 ps RMS), and SMBus-configurable control registers.

Technical Context

This device implements a dual-loop architecture: one PLL for clock synthesis and equalization compensation, and a bypass mode for low-latency distribution. The internal equalization compensates for high-frequency loss on long PCB traces, enabling robust Gen3 signaling even with >15-inch input trace lengths.

It supports two independent output enables (OE_0#, OE_1#) with internal pull-downs, configurable PLL bandwidth via PLL_BW_SEL, and SMBus slave interface (7-bit address 0xD4/D5) for runtime register access-including PLL bypass, bandwidth selection, and revision/vendor ID reads.

Key Specifications

Pinout & Package

Package: 20-pin TSSOP (173-mil width), Pb-free and RoHS-compliant (package code L).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242 and ICS843002AGI, PI6CEQ20200LE uniquely delivers HCSL-native outputs with on-die equalization and Gen3-compliant jitter-enabling drop-in replacement in space-constrained, long-trace PCIe designs without layout or supply voltage changes.

Availability

PI6CEQ20200LE is available at Aetrix Electronics and suitable for PCIe Gen3 server motherboards, embedded computing backplanes, network switch fabric cards, and industrial PCIe expansion chassis requiring stable component supply and long-term lifecycle support.

Supply support for PI6CEQ20200LE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-speed timing, interface, and signal-integrity solutions for datacenter, networking, and computing markets.

The PI6CEQ20200 belongs to Pericom's PCIe-optimized clock buffer product line, designed specifically to solve signal degradation and skew challenges in multi-lane, high-density PCIe Gen2/Gen3 systems.

FAQ

What is the function of the IRef pin, and how must it be connected?

The IRef pin sets the HCSL output current via an external 475Ω resistor to GND. This establishes ~14 mA drive strength, ensuring compliant differential swing (660–850 mV) and crossing voltage (250–550 mV). No connection or incorrect resistance causes output amplitude failure and PCIe link instability.

Does PI6CEQ20200LE support PCIe Gen3 at industrial temperature range?

No. Gen3 jitter compliance (0.61–1.0 ps RMS) is specified only for commercial temperature range (0°C to +70°C). At -40°C to +85°C, the device remains functional for Gen2 applications but does not meet Gen3 phase jitter mask requirements per specification Rev B.

How is SMBus communication configured, and what is the default address?

The device operates as an SMBus slave with fixed 7-bit address 0xD4 (write) / 0xD5 (read). No hardware address pins exist; configuration is performed via indexed block read/write protocol using register offsets 0x00–0x05 for control, revision, and vendor ID access.

Can PLL_BW_SEL be changed dynamically during operation, and what is the impact?

Yes - PLL_BW_SEL can be toggled in real time via pin or SMBus. Switching from low (0.25 MHz) to high (3 MHz) bandwidth improves SSC tracking but increases susceptibility to input jitter; the choice must match the source clock's spread-spectrum profile and system EMI targets.