Diodes Incorporated PI6CEQ20200LEX

Overview

PI6CEQ20200LEX from Pericom Semiconductor is a PCIe Gen2/Gen3-compliant zero-delay clock buffer with integrated equalization, dual HCSL outputs, 40ps typ cycle-to-cycle jitter, and 3.3V supply. It serves as a high-integrity clock distribution device in server motherboard timing trees, compensating for long-trace signal degradation via proprietary analog equalization.

For engineers reviewing the PI6CEQ20200LEX datasheet, PI6CEQ20200LEX pinout, PI6CEQ20200LEX application, or PI6CEQ20200LEX equivalent, key selection criteria include HCSL output compliance, PLL bandwidth selectability (0.25–3 MHz), <10ps output skew, SMBus-configurable control, and commercial-temperature operation (0°C to +70°C).

Technical Context

The PI6CEQ20200LEX employs a dual-loop PLL architecture with selectable bandwidth (0.25 MHz or 3 MHz) to track spread-spectrum clocking (SSC) across PCIe Gen2/Gen3 frequencies (90–110 MHz). Its internal equalizer enhances high-frequency content of degraded HCSL inputs before re-timing.

All outputs are current-mode HCSL drivers with 660–850 mV VOH, 0–150 mV VOL, and tightly controlled crossing voltage (250–550 mV). Output enable pins (OE_0#, OE_1#) support independent tri-state control with internal pull-downs, and the IRef pin sets output current via an external 475Ω resistor.

Key Specifications

Pinout & Package

Package: 20-pin TSSOP (173-mil width), Pb-free & RoHS-compliant (L package code), JEDEC MO-153F/AC compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242B and ICS843002AGI, the PI6CEQ20200LEX uniquely delivers native HCSL drive, on-die equalization, and dual-output skew control in a commercial-temp TSSOP-making it the only choice for Gen3-compliant, long-trace, low-skew server clock distribution without external components.

Availability

PI6CEQ20200LEX is available at Aetrix Electronics and suitable for PCIe Gen3 server motherboards, embedded computing backplanes, network switch timing subsystems, and enterprise storage controller designs requiring stable component supply and full production traceability.

Supply support for PI6CEQ20200LEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-speed timing, interface, and signal-integrity solutions for datacenter, networking, and computing markets.

The PI6CEQ20200LEX belongs to Pericom's PCIe-optimized clock buffer product line, engineered specifically to solve long-trace signal degradation and multi-lane skew challenges in Gen2/Gen3 server and storage platforms.

FAQ

What is the function of the IRef pin?

The IRef pin sets the output current of both HCSL drivers by connecting an external 475Ω resistor to GND. This establishes a 14 mA typical output drive strength, ensuring compliance with PCIe HCSL electrical specifications including VOH (660–850 mV) and VOL (0–150 mV). No internal current source is active without this resistor.

Does the PI6CEQ20200LEX support PCIe Gen3 spread-spectrum clocking (SSC)?

Yes - the device supports SSC tracking in both PLL bandwidth modes. With PLL_BW_SEL = 1, the 3 MHz loop bandwidth enables fast response to ±0.5% SSC modulation; with PLL_BW_SEL = 0, the 0.25 MHz bandwidth provides lower jitter for static or shallow-modulation sources. Gen3 performance is validated only within the commercial temperature range (0°C to +70°C).

Can the SMBus interface be used to disable the PLL and operate in bypass mode?

Yes - the SMBus Control Register (Data Byte 0, Bit 0) allows software-controlled PLL bypass. When enabled, the device routes the input clock directly to outputs with 4.0 ns propagation delay (vs. 650 ps in PLL mode), preserving input jitter but eliminating re-timing benefits. This mode is useful for debug or legacy Gen1 systems where PLL lock instability occurs.

How are the analog and digital power/ground domains separated on this device?

VDDA (Pin 20) and GNDA (Pin 19) are dedicated analog/PLL supply and ground pins, physically isolated from digital VDD (Pins 5,9,12,16) and GND (Pins 6,15). This separation minimizes noise coupling into the sensitive PLL and equalizer circuits, directly contributing to the device's 40 ps cycle-to-cycle jitter and sub-1 ps RMS phase jitter performance.