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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Diodes Incorporated PI6CEQ20200LIE

Name: PI6CEQ20200LIE
Brand: Diodes Incorporated
SKU: PI6CEQ20200LIE
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: PI6CEQ20200LIE

Manufacturer:: Diodes Incorporated

Category:: Application Specific Clock/Timing

Package:: 20-TSSOP (0.173", 4.40mm Width)

Datasheet:: PI6CEQ20200LIE.pdf

Description:: IC CLOCK GENERATOR 20-TSSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

PI6CEQ20200LIE from Pericom Semiconductor is a PCIe Gen2/Gen3-compliant zero-delay clock buffer with integrated equalization, dual HCSL outputs, 40ps typ cycle-to-cycle jitter, and 3.3V supply. It serves as a high-integrity clock distribution device in PCIe root complex and endpoint timing paths, supporting long-trace input signal recovery in server backplanes.

For engineers reviewing the PI6CEQ20200LIE datasheet, PI6CEQ20200LIE pinout, PI6CEQ20200LIE application, or PI6CEQ20200LIE equivalent, key selection criteria include HCSL output compliance, PLL bandwidth selectability (0.25–3 MHz), industrial temperature range (−40°C to +85°C), SMBus-configurable control registers, and <10ps output-to-output skew.

Technical Context

The PI6CEQ20200LIE implements a dual-loop PLL architecture with selectable bandwidth (PLL_BW_SEL pin) to optimize spread-spectrum clock (SSC) tracking for PCIe Gen2 (100 MHz) and Gen3 (100 MHz) reference clocks. Its proprietary equalization compensates for high-frequency loss on long PCB traces feeding the SRCIN/SRCIN# differential inputs.

It supports SMBus slave-mode configuration via SCLK/SDATA pins, enabling runtime control of PLL bypass, bandwidth, and register readback. All outputs are current-mode HCSL with 475Ω IRef termination, delivering 660–850 mV VOH and <150 mV VOL into 50Ω loads.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Frequency	90–110 MHz - matches PCIe Gen2/Gen3 100 MHz reference clock with ±10% margin for SSC modulation.
Cycle-to-Cycle Jitter	40 ps (typ) - ensures timing margin compliance for PCIe Gen3 8 GT/s data rates.
Output-to-Output Skew	<10 ps - enables simultaneous clocking of multiple PCIe lanes without inter-lane timing misalignment.
Supply Voltage	3.135–3.465 V - tight 3.3V tolerance supports stable operation under noisy board-level power conditions.
Operating Temperature	−40°C to +85°C - qualified for industrial-grade embedded computing and networking equipment.
PLL Bandwidth	0.25–3 MHz (selectable) - allows trade-off between SSC tracking fidelity and jitter attenuation.
HCSL Output Drive	14 mA typical - sustains valid HCSL waveform integrity into standard 50Ω transmission lines.

Pinout & Package

Package: 20-pin TSSOP (173-mil width), Pb-free & RoHS-compliant (L package code), thermal pad not present.

Pin/Terminal	Circuit Role	Design Meaning
1	PLL_BW_SEL	CMOS input selecting PLL loop bandwidth (low=0.25–1 MHz, high=1.3–3 MHz) for optimal SSC tracking.
2,3	SRCIN, SRCIN#	Differential HCSL input pair accepting degraded PCIe reference clock; internal equalization restores signal integrity.
4,17	OE_0#, OE_1#	Active-low output enable controls tri-state of CLK0/CLK0# and CLK1/CLK1# independently; internal pull-down ensures default disable.
7,8,13,14	CLK0, CLK0#, CLK1, CLK1#	Four-pin HCSL differential output pairs (two independent channels), each with matched routing requirements.
10,11	SDATA, SCLK	SMBus interface pins (slave-only); support indexed block read/write for runtime PLL and bypass configuration.
18	IRef	Analog current reference pin; connects to 475Ω resistor to GND to set HCSL output drive strength.
5,9,12,16,20	VDD / VDDA	Digital (VDD) and analog/PLL (VDDA) 3.3V supplies - require separate decoupling to minimize noise coupling.
6,15,19	GND / GNDA	Digital ground (GND) and analog/PLL ground (GNDA) - must be connected at single point near device for low-noise PLL operation.

Key Features

Feature	Design Value
Integrated Equalization	Compensates for ≥15 dB high-frequency loss on input trace, enabling reliable PCIe Gen3 clock recovery from >15-inch FR4 runs.
Dual PLL Bandwidth Selection	Hardware-selectable (pin) and SMBus-controllable bandwidths allow optimization for different SSC profiles without firmware change.
HCSL Output Compliance	Meets PCIe Gen2/Gen3 HCSL electrical specs: VOH 660–850 mV, VOL <150 mV, ΔVCROSS ≤140 mV, duty cycle 47–53%.
SMBus Slave Interface	7-bit address 0xD4/D5 supports runtime reconfiguration of PLL bypass, bandwidth, and register readback without reset.
Industrial Temperature Range	−40°C to +85°C operation validated per JEDEC JESD22-A108, suitable for uncooled network line cards and edge servers.

Applications

PCIe Server Backplane Clocking

Embedded Computing PCIe Slot Timing

Use Scenario: Distributing 100 MHz PCIe reference clock across 12+ slots in a 2U rack server with >10-inch input trace length.

IC Role / Device Role / Timing Role: Zero-delay buffer with equalization restoring signal integrity before fanout to slot connectors.

Use Value: Eliminates need for external equalizer IC or trace-length matching, reducing BOM count and layout complexity.

Use Scenario: Providing synchronized HCSL clocks to dual x4 PCIe endpoints on an industrial GPU-accelerated edge AI module.

IC Role / Device Role / Timing Role: Dual-channel clock buffer enabling independent enable/disable of each PCIe link's reference clock.

Use Value: Supports dynamic power gating of PCIe links while maintaining sub-10ps inter-channel skew for deterministic latency.

Networking Switch Fabric Timing

High-Density Storage Controller Clocking

Use Scenario: Driving 100 MHz reference clocks to 8x 25G Ethernet PHYs and 4x PCIe Gen3 controllers in a Layer 3 switch ASIC card.

IC Role / Device Role / Timing Role: Low-jitter clock distribution hub with SMBus-configurable PLL bypass for system-level timing calibration.

Use Value: Enables field-upgradable timing behavior (e.g., switching between PLL and bypass modes) without hardware revision.

Use Scenario: Clocking NVMe SSD controller and PCIe switch in a 2U JBOD enclosure with mixed commercial/industrial ambient conditions.

IC Role / Device Role / Timing Role: Industrial-temp-rated buffer ensuring PCIe Gen3 timing compliance across −40°C startup and +85°C sustained operation.

Use Value: Guarantees 40ps cycle-to-cycle jitter and <10ps skew over full temperature range, preventing link training failures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IDT8T49N242B	LVDS outputs (not HCSL); supports PCIe Gen4; higher ICC (85 mA); requires external VTT termination.	Requires redesign of output termination network; not drop-in for HCSL-referenced FPGA/ASIC receivers.	Select only if upgrading to Gen4 and LVDS-compatible downstream devices are used.
ICS8430M	Single HCSL output; no equalization; 60ps cycle-to-cycle jitter; commercial temp only (0°C to +70°C).	Lacks signal restoration capability and industrial temp rating; insufficient for long-trace or extended ambient use.	Acceptable only for short-trace, cost-sensitive commercial systems with no thermal or signal integrity constraints.

Compared with IDT8T49N242B and ICS8430M, the PI6CEQ20200LIE uniquely delivers HCSL-native outputs with on-die equalization and industrial temperature support-enabling direct replacement of legacy buffers in thermally demanding PCIe Gen2/Gen3 infrastructure without layout or termination changes.

Availability

PI6CEQ20200LIE is available at Aetrix Electronics and suitable for PCIe server backplanes, industrial embedded computing platforms, and high-density networking switches requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6CEQ20200LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-speed timing, interface, and signal integrity solutions for datacenter and communications infrastructure.

The PI6CEQ20200 belongs to Pericom's PCIe-optimized clock buffer product line, engineered specifically to solve signal degradation and jitter accumulation in multi-slot, high-speed serial interconnect systems.

FAQ

What is the function of the IRef pin, and how must it be connected?

The IRef pin sets the HCSL output drive current via an external 475Ω resistor to GND. This resistor establishes ~14 mA output current, ensuring compliant VOH (660–850 mV) and VOL (<150 mV) levels. No capacitor or active circuitry is permitted on IRef; deviation from 475Ω directly alters output amplitude and crossing point voltage.

Can the PI6CEQ20200LIE operate in PCIe Gen3 mode at industrial temperature?

No. While the PI6CEQ20200LIE is rated for −40°C to +85°C operation, Gen3 performance (including jitter mask compliance per PCI-SIG) is specified only for commercial temperature (0°C to +70°C). At industrial temperatures, it remains fully functional for Gen2 applications with verified 40ps cycle-to-cycle jitter and <10ps skew.

How does the SMBus interface interact with the PLL_BW_SEL pin?

The PLL_BW_SEL pin provides hardware-selectable bandwidth (low/high), while the SMBus Control Register Bit 1 (PLL_BW_SEL) offers software override. When SMBus control is enabled (SMB_EN = 1), the register value takes precedence; otherwise, the pin state determines bandwidth. Both methods configure the same PLL loop filter coefficients.

Is there a recommended termination network for the HCSL outputs?

Yes. Each HCSL differential pair (CLK0/CLK0#, CLK1/CLK1#) requires 50Ω series termination at the source (near PI6CEQ20200LIE) and 50Ω parallel AC-coupled termination at the receiver. The datasheet specifies Rs = 33Ω and Rp = 49.9Ω with 2pF load capacitance as the test condition for AC characteristics, and this network ensures compliance with PCIe HCSL eye diagram and jitter requirements.

PI6CEQ20200LIE Specifications

Product attributes: Attribute value

Manufacturer:: Diodes Incorporated

Series:: -

Package/Case:: 20-TSSOP (0.173", 4.40mm Width)

Packaging:: Tube

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: PCI Express (PCIe)

Input:: HCSL

Output:: HCSL

Number of Circuits:: 1

Ratio - Input:Output:: 1:2

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 110MHz

Voltage - Supply:: 3.135V ~ 3.465V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 20-TSSOP

PI6CEQ20200LIE FAQ

1.How can I place an order for PI6CEQ20200LIE through Aetrix?

Please submit a Request for Quotation (RFQ) for PI6CEQ20200LIE on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PI6CEQ20200LIE reliable?

The price and inventory of PI6CEQ20200LIE are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6CEQ20200LIE is usually 5 days.

3.What payment methods are accepted for PI6CEQ20200LIE?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6CEQ20200LIE transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PI6CEQ20200LIE?

PI6CEQ20200LIE orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PI6CEQ20200LIE order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PI6CEQ20200LIE?

For technical support, including PI6CEQ20200LIE datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6CEQ20200LIE requirements.

6.How does Aetrix verify that PI6CEQ20200LIE is sourced from the original manufacturer or authorized distributors?

All PI6CEQ20200LIE products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6CEQ20200LIE meets industry standards.

7.What is the process for return or replacement of PI6CEQ20200LIE?

All PI6CEQ20200LIE units undergo pre-shipment inspection (PSI). If there is an issue with PI6CEQ20200LIE, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PI6CEQ20200LIE part is unused and in its original packaging.

Return procedure for PI6CEQ20200LIE:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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