Diodes Incorporated PI6CEQ20200LIEX

Overview

PI6CEQ20200LIEX from Pericom Semiconductor is a PCIe Gen2/Gen3-compliant zero-delay clock buffer with integrated equalization, dual HCSL outputs, 40ps typ cycle-to-cycle jitter, <10ps output-to-output skew, and 3.3V operation-designed for high-integrity clock distribution in server backplanes where input traces exceed 15 inches.

For engineers reviewing the PI6CEQ20200LIEX datasheet, PI6CEQ20200LIEX pinout, PI6CEQ20200LIEX application, or PI6CEQ20200LIEX equivalent, key selection criteria include Gen3-compatible phase jitter (≤1.0 ps RMS), dual PLL bandwidth selection (0.25–3 MHz), SMBus-configurable control, HCSL output compliance, and industrial temperature support (−40°C to +85°C).

Technical Context

The device implements two independent PLLs-one for each HCSL output pair-with selectable loop bandwidth (0.25 MHz or 3 MHz) via PLL_BW_SEL to optimize spread-spectrum clock (SSC) tracking across Gen2/Gen3 frequency ranges (90–110 MHz). Internal equalization compensates for channel loss up to 15 dB at 5 GHz.

It operates in either PLL mode (650 ps propagation delay) or bypass mode (4.0 ns delay), with SMBus slave interface (7-bit address 0xD4/D5) enabling runtime register access to control PLL bypass, bandwidth, and revision identification-while OE_0# and OE_1# provide hardware-level output enable for power sequencing.

Key Specifications

Pinout & Package

Package: 20-pin TSSOP (173-mil width), Pb-free & RoHS-compliant (package code L), thermal pad not included.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242A and Si53302-D-GM, PI6CEQ20200LIEX provides hardware-selectable PLL bandwidth and integrated equalization-reducing design complexity for Gen3-compliant PCIe fan-out without external components or runtime firmware overhead.

Availability

PI6CEQ20200LIEX is available at Aetrix Electronics and suitable for PCIe server backplanes, industrial embedded computing systems, and networking switch line cards requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6CEQ20200LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor was a fabless provider of high-speed interface and timing solutions, acquired by Diodes Incorporated in 2017; its timing portfolio continues under Diodes' Precision Timing Division.

The PI6CEQ20200 belongs to Pericom's PCIe-optimized clock buffer product line, engineered specifically for Gen2/Gen3 signal integrity challenges in dense, high-speed backplane and mezzanine applications.

FAQ

What is the function of the IRef pin, and what resistor value is required?

The IRef pin sets the HCSL output current via an external resistor to GND. A 475Ω ±1% resistor is required to achieve nominal 14 mA output drive strength, ensuring compliance with JEDEC HCSL voltage swing (660–850 mV) and crossing point (250–550 mV) specifications across temperature and voltage.

Does PI6CEQ20200LIEX support PCIe Gen4 or Gen5 timing requirements?

No. The PI6CEQ20200LIEX is specified only for PCIe Gen2/Gen3 (90–110 MHz input), with Gen3 phase jitter validated up to 1.0 ps RMS. It does not meet Gen4 (16 GT/s) or Gen5 (32 GT/s) jitter masks or frequency range requirements, and lacks support for 128b/130b encoding clocking schemes.

How does the PLL_BW_SEL pin affect spread-spectrum clock tracking performance?

When PLL_BW_SEL = 0, the PLL loop bandwidth is 0.25–1 MHz-optimized for Gen2 SSC profiles with slower modulation rates. When PLL_BW_SEL = 1, bandwidth increases to 1.3–3 MHz-enabling tighter tracking of Gen3 SSC with higher-frequency modulation, reducing residual jitter by up to 40% compared to low-BW mode under identical input conditions.

Can OE_0# and OE_1# be used simultaneously to gate both outputs, and what is the enable/disable timing?

Yes, OE_0# and OE_1# operate independently and can be asserted simultaneously to tri-state both HCSL output pairs. OE enable/disable time is 100 ns maximum, with internal pull-downs ensuring outputs remain enabled during power-up or floating control states-critical for deterministic PCIe link initialization sequences.