Diodes Incorporated PI6CFGL201BZDIE

Overview

PI6CFGL201BZDIE from Diodes Incorporated is a 2-output, low-power PCIe Gen 1/2/3 clock generator with integrated 100Ω HCSL/LVDS-compatible outputs, 25MHz crystal/reference input, and programmable spread spectrum (–0.25%, –0.5%, off). It delivers 100MHz differential clocks with typical cycle-to-cycle jitter of 30ps and includes a 1.8V LVCMOS REF1.8 output for system timing reference in high-speed server and storage platforms.

For engineers reviewing the PI6CFGL201BZDIE datasheet, PI6CFGL201BZDIE pinout, PI6CFGL201BZDIE application, or PI6CFGL201BZDIE equivalent, key selection criteria include PCIe 3.0 phase jitter compliance (0.46ps rms), dual OE# control for dynamic clock gating, SMBus-programmable slew rate and amplitude, and industrial-temperature operation in 24-TQFN package.

Technical Context

The PI6CFGL201BZDIE integrates a PLL-based frequency synthesis architecture optimized for PCIe clock distribution, accepting a 25MHz fundamental-mode crystal or external reference and generating two synchronized 100MHz differential outputs. Its internal termination eliminates external resistors, ensuring Zo = 100Ω across both HCSL and LVDS-compatible loads.

It supports three spread-spectrum modulation modes via hardware latch (SS_EN_tri) or SMBus software control, with configurable output amplitude (0.6–0.9V), slew rate (1.5/3.0V/ns per output pair), and REF1.8 output slew (0.9–1.8V/ns). Power management includes CKPWRGD_PD#-controlled startup/suspend and OE#-gated output enable with ≤3-clock latency.

Key Specifications

Pinout & Package

Package: 24-pin Thin Quad Flat No-Lead (TQFN), 4mm × 4mm, 0.5mm pitch, exposed thermal pad (connected to GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generation applications.

Compared with ICS843002AGI-01LFT and Si53301-A01AGM, the PI6CFGL201BZDIE uniquely balances PCIe Gen 3 compliance, dual-output independence, hardware spread-spectrum control, and integrated termination-making it optimal for cost- and space-constrained PCIe 3.0 add-in cards and storage controllers where BOM reduction and thermal efficiency are critical.

Availability

PI6CFGL201BZDIE is available at Aetrix Electronics and suitable for PCIe Gen 3 server backplanes, enterprise NVMe SSD controllers, and RAID controller cards requiring stable component supply, industrial-temperature operation, and long-term lifecycle continuity.

Supply support for PI6CFGL201BZDIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance timing, power management, and signal integrity solutions for industrial, computing, and communications markets.

The PI6CFGL201BZDIE belongs to Diodes' PCIe-optimized clock generator product line, designed specifically to replace legacy Pericom devices with enhanced jitter performance, lower power, and simplified layout-targeting next-generation data center and storage infrastructure.

FAQ

What crystal specifications are required for stable operation?

The PI6CFGL201BZDIE requires a 25MHz fundamental-mode crystal with 18pF load capacitance (CL), such as SaRonix-eCera FL2500047 or FY2500091. Equivalent Series Resistance must be ≤40Ω, and frequency tolerance should be ±20ppm or better. External load capacitors C1/C2 are recommended at 27pF each for CL=18pF crystals, adjustable based on board parasitics.

How does the CKPWRGD_PD# pin affect device initialization?

CKPWRGD_PD# is an active-low power-good input with internal pull-up. On first high assertion, it latches SADR, SS_EN_tri, and OE# states and starts PLL lock sequence. When held low, the device enters full power-down mode (IDDPD = 1.3–1.8mA) and disables all outputs and REF1.8. Subsequent high assertions exit power-down and re-enable clocks without full reset.

Can the REF1.8 output operate independently of the main clock outputs?

Yes. REF1.8 is a dedicated 25MHz LVCMOS output with independent SMBus control (BYTE 3 register) for slew rate, power-down, and enable. It remains functional even when CLK0/CLK1 are disabled via OE# or power-down mode, enabling use as a system-wide timing reference for management controllers or watchdog circuits.

What are the key layout considerations for minimizing jitter in PCIe applications?

Place the 25MHz crystal within 5mm of XTAL_IN/XTAL_OUT with symmetric traces, avoid routing near switching noise sources, and connect the exposed thermal pad directly to a solid GND plane. Use controlled-impedance 100Ω differential pairs for CLK0/CLK1 with minimal stubs, and decouple VDDA3.3 and VDDO1.8 with 100nF + 10µF capacitors placed <2mm from respective pins.