Diodes Incorporated PI6CFGL201BZDIEX

Overview

PI6CFGL201BZDIEX from Diodes Incorporated is a 2-output, low-power PCIe Gen 1/2/3 clock generator with integrated 100Ω HCSL/LVDS-compatible outputs, 25MHz crystal/reference input, and programmable spread spectrum (–0.25%, –0.5%, off). It delivers 100MHz differential clocks with typ. 30ps cycle-to-cycle jitter and includes a 1.8V LVCMOS REF1.8 output for system timing reference in high-speed server and storage applications.

For engineers reviewing the PI6CFGL201BZDIEX datasheet, PI6CFGL201BZDIEX pinout, PI6CFGL201BZDIEX application, or PI6CFGL201BZDIEX equivalent, key selection criteria include PCIe 3.0 phase jitter compliance (0.46ps rms), dual OE# control for dynamic clock gating, SMBus-programmable slew rate and amplitude, and 24-pin TQFN package thermal performance (θJA = 54.4°C/W).

Technical Context

The PI6CFGL201B employs a PLL-based architecture with configurable loop bandwidth (2–4MHz) optimized for PCIe Gen 3 CDR requirements, supporting both crystal (25MHz fundamental) and external reference inputs. Its dual-output stage integrates on-die 100Ω termination and independent OE# pins for per-channel power management.

Spread spectrum modulation is latched at power-up via SS_EN_tri and can be overridden via SMBus register B1[4:3]; REF1.8 output is enabled only after first CKPWRGD_PD# assertion and supports Wake-on-LAN functionality via register B3[5]. All digital I/Os are 3.3V-tolerant with Schmitt-trigger inputs except SMBus lines.

Key Specifications

Pinout & Package

Package: 24-pin Thin Quad Flat No-Lead (TQFN-ZD), 4mm × 4mm × 0.75mm, exposed thermal pad (connected to GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generation applications.

Compared with IDT8T49N242A-XXLFT and Si53320-D-GM, the PI6CFGL201BZDIEX uniquely combines dual OE# control, REF1.8 output, and SMBus-configurable slew/amplitude in a single 24-pin TQFN - enabling compact, firmware-adaptable PCIe clocking without external components.

Availability

PI6CFGL201BZDIEX is available at Aetrix Electronics and suitable for enterprise SSD controllers, PCIe switch modules, AI accelerator cards, and industrial embedded riser boards requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6CFGL201BZDIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-reliability timing, power management, and signal integrity solutions for industrial and computing markets.

The PI6CFGL201B belongs to Diodes' Pericom-branded PCIe clock generator product line, designed specifically for low-jitter, low-power, and pin-efficient clock distribution in Gen 1–3 PCIe systems with minimal external component count.

FAQ

What is the function of the SADR/REF1.8 pin?

The SADR/REF1.8 pin serves a dual role: during power-up, it latches the SMBus slave address (1101000b or 1101010b) based on its logic level; after startup, it functions as a 1.8V LVCMOS reference clock output (25MHz) with programmable slew rate and Wake-on-LAN enable via SMBus register B3. Internal pull-down ensures default address selection if left unconnected.

How does spread spectrum control work on the PI6CFGL201BZDIEX?

Spread spectrum is selected at power-up via the SS_EN_tri pin (0 = off, M = –0.25%, 1 = –0.5%) and can be overridden dynamically using SMBus register B1[4:3]. The modulation is triangular at 30–33kHz, reducing EMI peaks without affecting PCIe link stability. No external components are required - all control is internal to the device.

Can the PI6CFGL201BZDIEX drive LVDS receivers directly?

Yes - the PI6CFGL201BZDIEX's HCSL outputs are LVDS-compatible when terminated with 100Ω differential load. Diodes' datasheet provides explicit LVDS interface schematics: use 140Ω series resistors (R7a/R7b) if the receiver has internal termination, or 75Ω (R8a/R8b) if it does not. Common-mode voltage is maintained at 1.2V, matching standard LVDS input thresholds.

What is the startup behavior after CKPWRGD_PD# assertion?

Upon first rising edge of CKPWRGD_PD#, the device samples SADR, SS_EN_tri, and OE# states, powers up the PLL, and stabilizes outputs within 1ms. REF1.8 begins toggling only after this sequence completes. Subsequent low-to-high transitions of CKPWRGD_PD# exit power-down mode and restore outputs in ≤300μs, with no re-latching of configuration pins.