Diodes Incorporated PI6CFGL202BLIE

Overview

PI6CFGL202BLIE from Diodes Incorporated is a low-power PCIe 3.0-compliant clock generator with two HCSL differential outputs, designed for EMI reduction in PC and embedded systems. It accepts a 25 MHz crystal or single-ended clock input, generates 25/100/125/200 MHz outputs, supports -0.5%/-0.75% spread spectrum, and operates across industrial temperature range (-40°C to +85°C).

For engineers reviewing the PI6CFGL202BLIE datasheet, PI6CFGL202BLIE pinout, PI6CFGL202BLIE application, or PI6CFGL202BLIE equivalent, key selection criteria include PCIe Gen 3 phase jitter compliance (0.36 ps rms), cycle-to-cycle jitter (50 ps typ), output voltage swing (300 mV), spread select via SS0/SS1 pins, and independent 1.05–3.3 V output supply.

Technical Context

The PI6CFGL202BLIE implements a proprietary PLL architecture optimized for PCIe 3.0 timing integrity, with a PLL bandwidth of 2–4 MHz and CDR reference at 10 MHz. It supports triangular spread modulation at 30–33 kHz and delivers phase jitter of ≤1 ps rms in PCIe Gen 3 high-frequency band (1.5 MHz–50 MHz).

Frequency and spread are selected via hardwired logic pins (S1/S0 and SS1/SS0), eliminating I²C/SMBus dependency. Output drivers are configurable as HCSL or LVDS-compatible, with dedicated VDDO (1.05–3.3 V) and VDDA3.3 (3.0–3.6 V) rails enabling power domain isolation between analog PLL core and digital outputs.

Key Specifications

Pinout & Package

Package: 16-pin TSSOP (L16), Pb-free and RoHS 3 compliant, 173 mil wide.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with IDT8T49N242B and Si53320-D-GM, the PI6CFGL202BLIE offers hardware-configurable spread spectrum and dual-voltage outputs without serial interface overhead-ideal for cost-sensitive, fixed-configuration PCIe platforms where board space and BOM count are constrained.

Availability

PI6CFGL202BLIE is available at Aetrix Electronics and suitable for server motherboard clocking, embedded PCIe storage controllers, and industrial PC expansion requiring stable component supply, RoHS 3 compliance, and industrial temperature operation.

Supply support for PI6CFGL202BLIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in power management, signal integrity, and timing solutions for industrial, computing, and communications markets.

The PI6CFGL202BLIE belongs to Diodes' Pericom-branded timing product line, engineered specifically for PCIe 3.0 and Ethernet reference clock generation with emphasis on low jitter, spread spectrum EMI reduction, and simplified hardware configuration.

FAQ

What crystal specifications are required for stable operation?

The PI6CFGL202BLIE requires a 25 MHz parallel-resonant crystal with 18 pF load capacitance, ±20 ppm stability, and CL=18 pF (e.g., SaRonix-eCera FL2500047). External load capacitors C1/C2 must be set to 27 pF each to match the crystal's specified CL, accounting for PCB parasitics (Cb ≈ 2–4 pF) and chip input capacitance (Cj ≈ 3–5 pF).

Can the PI6CFGL202BLIE drive LVDS inputs directly?

Yes - its HCSL outputs are LVDS-compatible when terminated with 100 Ω differential loads and biased at 1.2 V common-mode. For receivers without internal termination, external 140 Ω Thevenin termination (R7a/R7b) and 0.1 µF AC-coupling capacitors are recommended per Diodes Application Note AN-41024.

How does spread spectrum selection affect PCIe link reliability?

Spread spectrum reduces peak EMI energy by spreading clock energy across a narrow band (±0.5% or ±0.75%), but introduces slight phase modulation. The PI6CFGL202BLIE maintains PCIe Gen 3 phase jitter compliance (≤1 ps rms) under all spread modes due to its optimized PLL loop filter and low-noise VCO design - verified per Intel Clock Jitter Tool calculations.

What is the purpose of separate VDDA3.3, VDDDIG3.3, and VDDO supply pins?

VDDA3.3 powers the analog PLL core for low-phase-noise operation; VDDDIG3.3 supplies digital logic (S0/S1/SS0/SS1/OE); VDDO sets output driver voltage (1.05–3.3 V). This separation prevents digital switching noise from coupling into the PLL, preserving <1 ps rms jitter performance - confirmed by measurement under full-load conditions.