Diodes Incorporated PI6CFGL401BZHIEX

Overview

PI6CFGL401BZHIEX from Pericom Semiconductor is a 4-output, low-power PCIe Gen 1/2/3 clock generator with integrated 100Ω HCSL/LVDS-compatible differential outputs, 25MHz crystal/reference input, and programmable spread spectrum (–0.25%, –0.5%, off). It delivers 100MHz outputs with <50ps cycle-to-cycle jitter and supports industrial temperature range (–40°C to +85°C) in a 32-pin TQFN package - used in server motherboard clock trees and PCIe switch timing subsystems.

For engineers reviewing the PI6CFGL401BZHIEX datasheet, PI6CFGL401BZHIEX pinout, PI6CFGL401BZHIEX application, or PI6CFGL401BZHIEX equivalent, key selection criteria include PCIe Gen3-compliant phase jitter (<1ps rms), SMBus-configurable slew rate and amplitude per output, REF1.8 LVCMOS output enable control, and CKPWRGD_PD#-managed power sequencing for reliable system boot timing.

Technical Context

The PI6CFGL401BZHIEX integrates a PLL-based clock synthesis architecture optimized for PCIe reference clock distribution, supporting both 25MHz crystal and external reference inputs. Its four differential outputs are individually enabled via OE# pins and SMBus registers, with each pair configurable for 0.6–0.9V amplitude and 0.7–4.0V/ns slew rate.

It implements dual-mode spread spectrum control - hardware-latched via SS_EN_tri at power-up and software-controllable via SMBus register B1[5:4] - while maintaining PCIe Gen3 phase jitter compliance (0.46ps rms, 12kHz–5MHz). The REF1.8 output operates as a 25MHz LVCMOS clock with programmable slew rate and Wake-on-LAN-aware power-down behavior.

Key Specifications

Pinout & Package

Package: 32-pin TQFN (ZH code), 5mm × 5mm × 0.8mm, exposed thermal pad, lead-free (RoHS-compliant).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe Gen3 clock generator applications.

Compared with IDT8T49N242A and Si53320-D-GM, the PI6CFGL401BZHIEX uniquely balances PCIe Gen3 jitter compliance, integrated 100Ω termination, per-output programmability, and a dedicated REF1.8 output - making it optimal for compact, cost-sensitive, and thermally constrained PCIe timing subsystems requiring flexible power management.

Availability

PI6CFGL401BZHIEX is available at Aetrix Electronics and suitable for server motherboard clock trees, PCIe switch timing modules, industrial embedded controllers, and workstation GPU expansion platforms requiring stable component supply and long-term lifecycle support.

Supply support for PI6CFGL401BZHIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-speed timing, interface, and signal-integrity solutions for datacenter, communications, and computing markets.

The PI6CFGL401BZHIEX belongs to Pericom's PCIe-optimized clock generator product line, designed specifically to replace legacy clock ICs in Gen1–Gen3 systems while minimizing layout complexity and power consumption.

FAQ

What is the function of the CKPWRGD_PD# pin?

The CKPWRGD_PD# pin serves dual functions: its first high assertion after power-up initiates device initialization and sampling of latched inputs (SADR, SS_EN_tri); when driven low, it places the device into power-down mode with only 1.3mA supply current. It features an internal pull-up resistor and must be synchronized with system power-rail sequencing to ensure deterministic startup behavior.

Can the PI6CFGL401BZHIEX drive LVDS receivers directly?

Yes - the PI6CFGL401BZHIEX's differential outputs are compatible with LVDS inputs when using the recommended external termination network: 140Ω across CLKx/CLKx# for receivers with internal 100Ω termination, or 75Ω with 0.1μF AC-coupling capacitors for unterminated receivers. Output common-mode voltage is 1.2V, matching standard LVDS thresholds.

How is spread spectrum controlled - hardware or software?

Spread spectrum is controlled both ways: hardware-latched via the SS_EN_tri pin at initial power-up (0 = off, M = –0.25%, 1 = –0.5%), and dynamically reconfigured via SMBus register B1[5:4] after initialization. Software control requires setting B1[5] = 1 first; both methods are mutually exclusive during operation and affect all four outputs simultaneously.

What is the purpose of the SADR/REF1.8 pin?

The SADR/REF1.8 pin serves two time-multiplexed roles: during the first 10ms after CKPWRGD_PD# goes high, it latches the SMBus slave address (1101000b or 1101010b); thereafter, it functions as the 25MHz 1.8V LVCMOS REF1.8 output. This dual use reduces pin count while providing a dedicated reference clock for auxiliary logic or firmware timing.