Diodes Incorporated PI6CG18200ZDIEX-13R

Overview

PI6CG18200ZDIEX-13R from Diodes Incorporated is a 2-output, 1.8V PCIe Gen1–Gen4 clock generator with crystal/CMOS 25 MHz input, dual low-power HCSL differential outputs at 100 MHz, and a buffered 1.8V LVCMOS reference output. It features programmable slew rate and amplitude per output, individual output enable control, spread-spectrum selection (0%, –0.25%, –0.5%), and SMBus or strapping-pin configuration. Used in high-speed server and storage motherboard clock trees.

For engineers reviewing the PI6CG18200ZDIEX-13R datasheet, PI6CG18200ZDIEX-13R pinout, PI6CG18200ZDIEX-13R application, or PI6CG18200ZDIEX-13R equivalent, key selection criteria include PCIe Gen4-compliant phase jitter (<0.5 ps RMS), differential cycle-to-cycle jitter <55 ps, output skew <50 ps, 3.3V-tolerant SMBus interface, and 24-pin 4×4 mm TQFN package with dedicated analog/digital power domains.

Technical Context

The PI6CG18200ZDIEX-13R integrates a proprietary low-jitter PLL architecture optimized for PCIe Gen4 compliance, with integrated oscillator circuitry supporting 25 MHz fundamental-mode crystals (8 pF load) or CMOS inputs. Its dual HCSL outputs are blocked until PLL lock is achieved, ensuring glitch-free startup.

Configuration is supported via tri-level SS_SEL_TRI pin for spread-spectrum selection at power-up or through a 3.3V-tolerant SMBus interface (400 kHz max) with latched address selection (SADR), enabling dynamic reconfiguration of slew rate, amplitude, and output enable states without reset.

Key Specifications

Pinout & Package

Package: 24-lead 4×4 mm TQFN (0.5 mm pitch), lead-free and halogen-free, with exposed thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with IDT8T49N242A and Si53320-D-GM, the PI6CG18200ZDIEX-13R uniquely combines PCIe Gen4 phase jitter compliance, dual independent output control, 3.3V-tolerant SMBus, and a buffered REFOUT-enabling flexible, future-proof clock tree design in thermally constrained server platforms.

Availability

PI6CG18200ZDIEX-13R is available at Aetrix Electronics and suitable for server motherboard clock trees, PCIe switch reference timing, high-density NVMe backplanes, and AI accelerator board timing requiring stable component supply and full lifecycle support.

Supply support for PI6CG18200ZDIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, communications, and industrial markets.

The PI6CG18200 belongs to Diodes' PCIe-optimized clock generator product line, designed specifically to meet stringent Gen4+ jitter, power, and configurability requirements in data center and AI infrastructure applications.

FAQ

What is the minimum startup time from power-up to stable 100 MHz HCSL output?

The PI6CG18200ZDIEX-13R requires 10 ms for full power stabilization and 20 ms for PLL lock after PD# de-assertion, resulting in a guaranteed 30 ms maximum startup time to stable, low-jitter 100 MHz outputs. Crystal stabilization adds ≤1.8 ms, making total time ≤32 ms under worst-case conditions.

Can the REFOUT pin be used as a standalone 25 MHz clock source for other ICs?

Yes-REFOUT delivers a buffered 1.8V LVCMOS 25 MHz clock with <1.5 ps RMS phase jitter and 45–55% duty cycle, directly usable by companion logic, microcontrollers, or ADCs. Its dedicated GND_REFOUT pin and internal 20 Ω output impedance ensure clean signal integrity without external buffering.

How does spread-spectrum modulation affect PCIe Gen4 link training?

Spread spectrum is applied only to the differential HCSL outputs (Q0/Q1), not REFOUT. With –0.25% or –0.5% triangular modulation at 30–33 kHz, it reduces EMI peaks without impacting PCIe Gen4 link training, as the instantaneous frequency deviation remains within Gen4's ±300 ppm tolerance and jitter integrals stay within spec.

Is the SMBus interface operational during power-down mode?

No-the SMBus interface is disabled in power-down mode (PD# = low). Configuration changes require exiting power-down first. However, strapping pins (SADR, SS_SEL_TRI, OE#) retain their latched state across PD# transitions, allowing hardware-defined behavior to persist without SMBus intervention.