Diodes Incorporated PI6CG182Q2ZDQEX

Overview

PI6CG182Q2ZDQEX from Diodes Incorporated is a 2-output, automotive-grade PCIe Gen4 clock generator with 1.8V supply, 25MHz crystal/CMOS input, and two low-power HCSL differential outputs (100MHz) featuring on-chip 50Ω termination. It delivers <50ps differential cycle-to-cycle jitter and <50ps output-to-output skew, and includes a buffered 1.8V LVCMOS reference output (REFOUT) with <1.5ps RMS phase jitter - deployed in ADAS domain controllers requiring AEC-Q100 Grade 2 timing integrity.

For engineers reviewing the PI6CG182Q2ZDQEX datasheet, PI6CG182Q2ZDQEX pinout, PI6CG182Q2ZDQEX application, or PI6CG182Q2ZDQEX equivalent, key selection criteria include PCIe Gen4 compliance, spread-spectrum control via SS_SEL_TRI, individual OE# enable for Q0/Q1, SMBus-configurable slew rate/amplitude, and integrated HCSL termination eliminating eight external resistors.

Technical Context

The PI6CG182Q2ZDQEX employs a proprietary PLL architecture optimized for PCIe Gen1–Gen4 common-clock mode, with lock time ≤20ms and startup time ≤10ms. Its dual HCSL outputs are blocked until PLL lock, ensuring glitch-free clock distribution during power-up sequencing in automotive infotainment and gateway ECUs.

Configuration is supported via strapping pins (SADR, SS_SEL_TRI, OE0#/OE1#, PD#) or 3.3V-tolerant SMBus interface (SCLK/SDATA), enabling runtime adjustment of spread spectrum (0%, −0.25%, −0.5%), output amplitude (0.6–0.9V), and slew rate (1.1–5.7 V/ns) - critical for EMI reduction and signal integrity tuning across varying PCB trace lengths and loads.

Key Specifications

Pinout & Package

Package: 24-lead 4×4mm TQFN (exposed pad), lead-free and halogen-free per RoHS 3 and Diodes' "Green" definition.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generation applications.

Compared with Si5332A-D-GM and ICS843002AGI-01LFT, the PI6CG182Q2ZDQEX uniquely combines AEC-Q100 Grade 2 qualification, PCIe Gen4 compliance, on-chip HCSL termination, and sub-50ps jitter in a 4×4mm TQFN - making it the only drop-in solution for new automotive PCIe Gen4 designs requiring zero external termination and guaranteed EMI reduction.

Availability

PI6CG182Q2ZDQEX is available at Aetrix Electronics and suitable for automotive ADAS domain controllers, PCIe-based telematics gateways, and autonomous driving compute modules requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant timing performance.

Supply support for PI6CG182Q2ZDQEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs, with strong focus on automotive, industrial, and computing markets - delivering high-reliability components certified to IATF 16949 and AEC-Q standards.

The PI6CG182Q2ZDQEX belongs to Diodes' Precision Clock Generation product line, engineered specifically for automotive PCIe timing applications demanding ultra-low jitter, spread-spectrum EMI control, and robust operation across extended temperature ranges.

FAQ

What is the function of the SADR/REFOUT pin?

The SADR/REFOUT pin serves a dual role: when configured as an input (via internal latch during power-up), it selects the SMBus slave address (0x68 or 0x6A); when configured as an output, it delivers a buffered 1.8V LVCMOS 100MHz reference clock (REFOUT) with <1.5ps RMS phase jitter. The mode is determined by the state of SADR at first PD# assertion and cannot be changed dynamically.

How does the PI6CG182Q2ZDQEX achieve PCIe Gen4 compliance?

It achieves PCIe Gen4 compliance through a proprietary low-noise PLL architecture delivering <50ps differential cycle-to-cycle jitter and <50ps output-to-output skew at 100MHz, along with integrated HCSL drivers meeting PCIe Gen4 AC timing and voltage swing specifications (VOH = 660–784mV, VOL = ±150mV). All parameters are validated per PCI-SIG test plans across −40°C to +105°C.

Can the spread spectrum be disabled after power-up?

Yes - spread spectrum can be disabled or reconfigured post-power-up via SMBus register Byte 1[5:4] (SSEN_SWCTR and SSENSW[1:0]). When SSEN_SWCTR = 1, software control overrides the SS_SEL_TRI pin setting, allowing dynamic EMI tuning during system operation without hardware modification or reset.

What is the purpose of the PD# pin's internal pull-up resistor?

The internal pull-up resistor on PD# ensures the device powers up in active mode (not deep sleep) when left unconnected, preventing unintended clock disable during boot. It also guarantees fast, deterministic exit from Power Down Mode: a rising edge on PD# initiates PLL restart and output enable within 300μs, synchronizing with system wake events like CAN bus activity or ignition-on signals.