Diodes Incorporated PI6CG184Q2ZHQEX

Overview

PI6CG184Q2ZHQEX from Diodes Incorporated is a 4-output, 1.8V automotive-grade PCIe Gen4 clock generator with integrated 100MHz low-power HCSL outputs, on-chip termination, and AEC-Q100 Grade 2 qualification. It accepts a 25MHz crystal or CMOS reference input, delivers differential cycle-to-cycle jitter <50ps, and supports spread-spectrum modulation (–0.25% or –0.5%) for EMI reduction in vehicle infotainment and ADAS timing systems.

For engineers reviewing the PI6CG184Q2ZHQEX datasheet, PI6CG184Q2ZHQEX pinout, PI6CG184Q2ZHQEX application, or PI6CG184Q2ZHQEX equivalent, this device requires attention to its 32-pin TQFN package, SMBus- or strapping-based configuration, individual output enable control, programmable slew rate per output, and differential output blocking until PLL lock - all critical for automotive board-level timing integrity and compliance validation.

Technical Context

The PI6CG184Q2ZHQEX employs a proprietary low-jitter PLL architecture locked to a 25MHz fundamental-mode crystal or CMOS input, generating four 100MHz HCSL outputs with on-die 50Ω source termination per leg. Its analog and digital power domains are segregated (VDDA, VDDO, VDD_DIG, VDD_REFOUT), enabling independent supply optimization and noise isolation.

Configuration is supported via tri-level SS_SEL_TRI pin for spread-spectrum selection at power-up and 3.3V-tolerant SMBus interface (address latched on SADR) for runtime register access-including per-output enable, slew rate, amplitude, and REFOUT control. Power-down mode is asserted via PD# with internal pull-up, and wake-on-LAN support is implemented through dedicated REFOUT control bits.

Key Specifications

Pinout & Package

Package: 32-lead, 5mm × 5mm, 0.5mm pitch TQFN with exposed thermal pad (RoHS-compliant, halogen-free).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe Gen4 clock generator applications.

Compared with Si5332A-D-GM and ICS843002AGI-01LFT, the PI6CG184Q2ZHQEX uniquely combines AEC-Q100 Grade 2 qualification, on-die HCSL termination, and selectable spread spectrum - making it the only drop-in solution for automotive PCIe Gen4 timing where BOM simplification, EMI compliance, and extended temperature operation are mandatory.

Availability

PI6CG184Q2ZHQEX is available at Aetrix Electronics and suitable for automotive infotainment systems, ADAS domain controllers, and telematics control units requiring stable component supply, full traceability, and long-term lifecycle support.

Supply support for PI6CG184Q2ZHQEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance, high-reliability solutions for automotive, industrial, and computing markets.

The PI6CG184Q2ZHQEX belongs to Diodes' PCIe Gen4 clock generator product line, engineered specifically for automotive-grade timing applications demanding ultra-low jitter, spread-spectrum EMI reduction, and AEC-Q100 qualification.

FAQ

What is the function of the SS_SEL_TRI pin?

The SS_SEL_TRI pin is a tri-level strapping input that selects spread-spectrum modulation amount at initial power-up: logic '0' disables spread spectrum, 'M' (mid-voltage ≈0.5×VDD) enables –0.25% modulation, and '1' enables –0.5% modulation. This setting is latched during power-on reset and cannot be changed dynamically without cycling PD#.

How does the PI6CG184Q2ZHQEX handle power-down and wake-on-LAN modes?

Asserting PD# low enters power-down mode, disabling all HCSL outputs and reducing total current to ≤1mA. When Byte 3, bit 5 is set to '1', REFOUT remains active in wake-on-LAN mode while Q-outputs stay off, drawing only 0.4–1mA IDDA_WL. REFOUT can then serve as a low-noise timing source for network recovery circuitry.

Can the REFOUT pin be used as a general-purpose LVCMOS clock buffer?

Yes - when SADR/REFOUT is configured as REFOUT (via internal pull-down), it delivers a buffered 25MHz LVCMOS output with <1.5ps RMS phase jitter, 45–55% duty cycle, and programmable slew rate (0.6–3.0V/ns). It operates from VDD_REFOUT (1.8V) and drives 20Ω output impedance into standard CMOS loads.

What is the significance of the separate VDDO and VDDA supply pins?

VDDO powers only the four HCSL output drivers, allowing independent voltage control and noise isolation from digital logic. VDDA supplies the PLL and oscillator circuitry, ensuring analog stability. Separating these rails minimizes coupling between high-speed switching outputs and sensitive PLL components - critical for achieving <0.5ps RMS phase jitter in automotive environments.