Diodes Incorporated PI6CG18801ZLIEX

Overview

PI6CG18801ZLIEX from Diodes Incorporated is an 8-output PCIe Gen1–Gen4 clock generator with on-chip HCSL termination, 1.8V supply, 25MHz crystal/CMOS input, and 100MHz differential outputs. It delivers <50ps cycle-to-cycle jitter, <60ps output-to-output skew, and supports spread-spectrum options (0%, –0.25%, –0.5%) for EMI reduction in high-speed server and storage platforms.

For engineers reviewing the PI6CG18801ZLIEX datasheet, PI6CG18801ZLIEX pinout, PI6CG18801ZLIEX application, or PI6CG18801ZLIEX equivalent, key selection criteria include PCIe Gen4 compliance, per-output enable/disable control via OE# pins, SMBus- or strapping-based configuration, 3.3V-tolerant SMBus interface, and integrated 50Ω on-die termination eliminating 32 external resistors.

Technical Context

The PI6CG18801 employs a proprietary PLL architecture optimized for PCIe timing budgets, achieving <0.5ps RMS phase jitter on the CMOS REFOUT and <50ps differential cycle-to-cycle jitter across all eight HCSL outputs. Its dual-mode reference path accepts either a 25MHz fundamental-mode crystal (8pF load) or CMOS clock input with 5ns max rise/fall time.

Configuration is supported via tri-level SS_SEL_TRI pin for spread-spectrum selection at power-up or through SMBus (400kHz max), with latched address selection on SADR pin and 7-bit slave address (0x68 or 0x6A). Power management includes PD#-controlled entry into low-current wake-on-LAN (1mA total IDD) or deep power-down (<1µA IDDO_PD) modes.

Key Specifications

Pinout & Package

PI6CG18801ZLIEX is housed in a 48-lead 6×6mm TQFN package with exposed thermal pad (ZLIEX suffix), supporting reflow-compatible assembly and efficient heat dissipation in dense PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generation applications.

Compared with IDT8T49N242B and Si53320-D-GM, the PI6CG18801ZLIEX uniquely integrates on-die HCSL termination and selectable spread-spectrum-reducing component count by 32 parts and enabling direct EMI compliance without additional circuitry-making it optimal for cost- and space-constrained PCIe Gen4 server and storage designs.

Availability

PI6CG18801ZLIEX is available at Aetrix Electronics and suitable for PCIe Gen4 server motherboards, enterprise NVMe SSDs, AI accelerator cards, and 5G fronthaul modules requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for PI6CG18801ZLIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, industrial, and communications markets.

The PI6CG18801 belongs to Diodes' PCIe-optimized clock generator product line, designed specifically to meet Gen1–Gen4 jitter, skew, and EMI requirements while minimizing board area and BOM cost through integration of termination and flexible configuration.

FAQ

What is the function of the SADR/REFOUT pin?

The SADR/REFOUT pin serves a dual role: during power-up, it latches the SMBus slave address (0x68 or 0x6A) based on its logic level; once configured, it can optionally function as a buffered 1.8V LVCMOS reference output (REFOUT) with <1.5ps RMS phase jitter, eliminating need for a separate reference buffer in timing-critical subsystems.

How does the PI6CG18801 ensure PCIe Gen4 compliance?

The PI6CG18801 meets PCIe Gen4 timing requirements through <50ps differential cycle-to-cycle jitter, <60ps output-to-output skew, and integrated spread-spectrum modulation (–0.25% or –0.5%). Its PLL architecture achieves <0.37ps RMS integrated phase jitter in Gen4 mode (10kHz–50MHz), verified per PCI-SIG specification and measured with ≥100k-cycle sampling.

Can the PI6CG18801 operate without an external crystal?

Yes - the PI6CG18801 accepts a 25MHz CMOS clock directly on the XTAL_IN/CLK pin, bypassing the crystal oscillator circuit. In this mode, the internal oscillator circuitry (including XTAL_OUT) is disabled, and the device locks to the external reference with identical jitter performance and full feature support including spread-spectrum and per-output control.

What happens to outputs during power-down mode?

When PD# is asserted low, all eight HCSL outputs (Q0+ to Q7+) drive low–low (not high-Z), REFOUT goes low, and supply currents drop to IDD_PD = 1mA typ. This behavior ensures deterministic signal states on downstream receivers during sleep states, preventing false triggering or undefined logic levels in PCIe link training sequences.