Diodes Incorporated PI6CG188Q2ZLQEX

Overview

PI6CG188Q2ZLQEX from Diodes Incorporated is an 8-output, automotive-grade PCIe Gen4 clock generator with 1.8V supply, 25MHz crystal/CMOS input, and eight differential low-power HCSL outputs featuring on-chip 50Ω termination. It delivers <50ps differential cycle-to-cycle jitter, <60ps output-to-output skew, and AEC-Q100 Grade 2 qualification for use in ADAS domain controllers and automotive infotainment backplanes.

For engineers reviewing the PI6CG188Q2ZLQEX datasheet, PI6CG188Q2ZLQEX pinout, PI6CG188Q2ZLQEX application, or PI6CG188Q2ZLQEX equivalent, key selection criteria include PCIe Gen4 timing compliance, spread-spectrum EMI reduction capability, individual output enable control, SMBus programmability, and integrated HCSL termination eliminating 32 external resistors.

Technical Context

The device implements a proprietary PLL architecture optimized for PCIe Gen1–Gen4 common-clock and separate-reference architectures, with configurable PLL bandwidth (2–5MHz) and CDR reference at 10MHz. It supports three spread-spectrum modulation depths (0%, –0.25%, –0.5%) via tri-level strapping or SMBus, and features dual configuration paths: hardware strapping pins for static setup and 3.3V-tolerant SMBus for dynamic runtime reconfiguration.

All eight HCSL outputs are gated until PLL lock detection, ensuring glitch-free startup. The buffered 1.8V LVCMOS REFOUT provides <1.5ps RMS phase jitter and serves as a low-noise reference for companion SerDes or PHYs, while independent OE# pins per output enable precise power sequencing in multi-rail automotive systems.

Key Specifications

Pinout & Package

Package: 48-lead 6mm × 6mm TQFN (exposed pad), RoHS-compliant, halogen- and antimony-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generation applications.

Compared with IDT8T49N242BGI800 and Si53320-D-GM, the PI6CG188Q2ZLQEX uniquely combines AEC-Q100 Grade 2 qualification, integrated HCSL termination, and selectable spread spectrum-enabling single-part compliance with automotive EMI, reliability, and layout constraints that alternatives cannot satisfy simultaneously.

Availability

PI6CG188Q2ZLQEX is available at Aetrix Electronics and suitable for ADAS domain controllers, automotive infotainment backplanes, and vehicle telematics gateways requiring stable component supply, long-term automotive lifecycle support, and AEC-Q100-compliant timing solutions.

Supply support for PI6CG188Q2ZLQEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-reliability power management, signal integrity, and timing solutions for automotive, industrial, and computing markets.

The PI6CG188Q product line delivers PCIe Gen1–Gen4 clock generators engineered specifically for automotive electronics, emphasizing AEC-Q100 qualification, low-jitter PLL design, and EMI-reduction features required in modern vehicle ECUs.

FAQ

What is the minimum startup time from power-on to stable 100MHz HCSL output?

The PI6CG188Q2ZLQEX achieves full startup-including crystal oscillation stabilization, PLL lock, and output enable-in ≤10ms after VDD reaches 1.7V. This is verified under worst-case conditions (–40°C, 1.7V supply, 25MHz crystal). The tLOCK specification confirms PLL lock occurs within 20ms, and tPDLAT guarantees differential outputs enable within 20–300µs after PD# deassertion.

Can the REFOUT pin be used simultaneously as SMBus address latch and clock output?

No. Pin 7 (SADR/REFOUT) operates in one mode only: when configured as SADR (default at power-up), it latches SMBus address and cannot output REFOUT; when configured as REFOUT via SMBus register Byte 0 Bit 7, it delivers the 1.8V LVCMOS buffered reference clock but loses SMBus address functionality. Mode selection is mutually exclusive and must be set before initialization.

How does the tri-level SS_SEL_TRI pin determine spread-spectrum depth?

SS_SEL_TRI (Pin 1) uses voltage thresholds relative to VDD: logic '0' (≤0.25×VDD) selects 0% spread; logic 'M' (0.4–0.6×VDD) selects –0.25%; logic '1' (≥0.75×VDD) selects –0.5%. These states are latched at first PD# high assertion and override SMBus-controlled spread settings until next power cycle or PD# reset.

What is the maximum allowable load capacitance on the XTAL_IN/CLK input?

The XTAL_IN/CLK input has a specified internal capacitance of 5pF and is designed for fundamental-mode 25MHz crystals with 8pF load capacitance. Total effective load-including PCB trace capacitance-must not exceed 10pF to maintain reliable oscillation margin and meet ±50ppm frequency accuracy over temperature and voltage. External loading beyond this risks startup failure or frequency drift.