Diodes Incorporated PI6CG330440AZUDIEX-13R

Overview

PI6CG330440AZUDIEX-13R from Diodes Incorporated is a 19-output PCIe 5.0/6.0 clock generator with on-chip termination, delivering 7 × 100MHz + 3 × 25MHz + 9 × selectable 25/100MHz differential HCSL outputs at 1.4V into PCIe-compliant loads. It supports 25MHz crystal or XO/TCXO/OCXO reference input, achieves <22fs RMS jitter (PCIe 6.0 Common Clock), and integrates dedicated PFT_IN/PFT_OUT pins for platform time synchronization.

For engineers reviewing the PI6CG330440AZUDIEX-13R datasheet, PI6CG330440AZUDIEX-13R pinout, PI6CG330440AZUDIEX-13R application, or PI6CG330440AZUDIEX-13R equivalent, this device addresses high-density server motherboard clocking, low-jitter PCIe Gen6 timing distribution, SMBus-configurable multi-frequency clock tree design, and platform time-aware system synchronization requirements.

Technical Context

The PI6CG330440A employs a dual-loop PLL architecture with integrated 85Ω HCSL drivers and programmable spread-spectrum control on 100MHz outputs. Its on-chip termination eliminates 80 external resistors, reducing layout complexity and improving signal integrity across 19 differential output pairs.

It implements three independent output enable mechanisms-dedicated OE# pins (7×), SMBus register bits (Bytes 0–2), and Side-Band Interface (SBI) shift/load control-with strict AND-gated logic ensuring glitch-free startup/shutdown. The PFT function is disabled by default for low-jitter 25MHz operation but can be enabled via SMBus Byte 49.

Key Specifications

Pinout & Package

Package: 100-contact, 8 mm × 8 mm UQFN (ZUD) with exposed thermal pad (EPAD).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with IDT8T49N242A and Si5341-A02879-GM, the PI6CG330440AZUDIEX-13R uniquely combines PCIe 6.0 jitter compliance, on-chip termination, PFT synchronization, and triple-enable safety - making it the only choice for high-density, time-aware Gen6 server clock trees.

Availability

PI6CG330440AZUDIEX-13R is available at Aetrix Electronics and suitable for server motherboard design, AI accelerator timing hubs, enterprise SSD controller development, and cloud-native network appliance production requiring stable component supply and long-term lifecycle assurance.

Supply support for PI6CG330440AZUDIEX-13R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for power management, signal integrity, and timing solutions.

The PI6CG330440A belongs to Diodes' PCIe-optimized clock generator product line, designed specifically for high-speed serial interface timing in next-generation data center and AI infrastructure.

FAQ

What is the maximum allowed reference clock frequency deviation for PCIe 6.0 compliance?

The PI6CG330440A supports 25MHz crystal or XO/TCXO/OCXO inputs with user-defined PPM stability. For PCIe 6.0 Common Clock compliance, the reference must meet ±50 ppm tolerance per Intel CK440Q specification. The device's <22fs RMS jitter is measured under this condition and verified in the DS45485 Rev 3-2 datasheet.

How does the PFT function affect jitter performance?

By default, the PFT function is bypassed to minimize jitter on the 25MHz outputs - achieving the specified <22fs RMS. When enabled via SMBus Byte 49, PFT_IN/PFT_OUT routing introduces additional path delay but maintains full PCIe 6.0 jitter compliance. The trade-off is deterministic latency vs. absolute minimum jitter.

Can the MXCK outputs be configured to run at frequencies other than 25MHz or 100MHz?

No. The MXCK[8:0] outputs are hardwired to select between 25MHz and 100MHz only, controlled by the MXCK_SEL_100# pin. There is no internal divider/multiplier or fractional synthesis capability for these outputs - they mirror one of the two primary generated frequencies.

Is the EPAD (C1) electrically connected internally, and how should it be handled on the PCB?

Yes, the EPAD (C1) is internally connected to GND and serves as the primary thermal and electrical ground path. It must be soldered to a solid copper thermal pad on the PCB with ≥4 thermal vias to an internal ground plane. Leaving it unconnected or floating violates thermal specs and risks output instability per DS45485 Section 7.2.