Diodes Incorporated PI6CG330440ZUDIEX

Overview

PI6CG330440 from Diodes Incorporated is a 19-output PCIe 5.0/6.0 clock generator with on-chip termination, delivering 7 dedicated 100MHz and 3 dedicated 25MHz differential HCSL outputs plus 9 multiplexable outputs (25/100MHz), RMS jitter <22fs at PCIe 6.0 common clock, and SMBus + Side-Band Interface programmability for server motherboard timing subsystems.

For engineers reviewing the PI6CG330440 datasheet, PI6CG330440 pinout, PI6CG330440 application, or PI6CG330440 equivalent, this device supports Intel CK440Q compliance, platform time input/output (PFT_IN/PFT_OUT), programmable spread-spectrum clocking (SSC), and tri-level SMBus address selection across 9 addresses - critical for high-density PCIe Gen6 timing architectures.

Technical Context

The PI6CG330440 integrates a low-jitter PLL with integrated 85Ω differential drivers and on-die 50Ω termination per output pair, eliminating 80 external resistors. It accepts a 25MHz crystal or XO/TCXO/OCXO reference and generates PCIe-compliant 100MHz (HCSL ±0.7V) and 25MHz (HCSL ±0.7V) clocks across 19 differential pairs.

Its dual control architecture combines hardware OE# pins (7 dedicated 100MHz outputs), SMBus register-based enable/disable (Bytes 0–2), and DB2000QL-compatible Side-Band Interface (SBI) with shift/load protocol - all requiring logical AND to enable any output, ensuring glitch-free startup/shutdown with <5ms power-up latency and <300μs output drive recovery.

Key Specifications

Pinout & Package

Package: 100-contact, 8 mm × 8 mm UQFN (ZUD) with exposed thermal pad (EPAD). Pin pitch: 0.4 mm. RoHS-compliant, halogen- and antimony-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with IDT8T49N242 and Si5341-A01A-GM, the PI6CG330440 uniquely delivers PCIe 6.0 jitter compliance (<22fs), on-die termination, and platform time I/O in a single UQFN package - reducing system-level timing validation effort and PCB layer count for Gen6 infrastructure.

Availability

PI6CG330440 is available at Aetrix Electronics and suitable for server motherboard design, AI accelerator card development, multi-socket platform time synchronization, and PCIe switch fabric timing requiring stable component supply and long-term lifecycle support.

Supply support for PI6CG330440 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for power management, signal integrity, and timing applications.

The PI6CG330440 belongs to Diodes' PCIe-optimized clock generator product line, engineered specifically for next-generation data center infrastructure requiring PCIe 5.0/6.0 compliance, ultra-low jitter, and scalable multi-device timing trees.

FAQ

What is the maximum supported input frequency for the XIN_CLKIN pin?

The XIN_CLKIN pin accepts only a 25MHz fundamental-mode crystal or single-ended clock input. It does not support higher-frequency references such as 100MHz or LVDS inputs. The internal oscillator circuit is optimized exclusively for 25MHz operation to meet PCIe CK440Q phase noise requirements.

Can the PFT_IN/PFT_OUT function be disabled to reduce power consumption?

Yes. The PFT function can be bypassed via SMBus register Byte 49, which disables the platform time circuitry and routes the internal 25MHz clock directly to PFT_OUT/PFT_OUT#. This reduces dynamic power by ~12mW while maintaining low-jitter 25MHz output for non-time-sync applications.

How many PI6CG330440 devices can share one SMBus controller?

Up to nine devices can share one SMBus controller using the tri-level address inputs (SMB_ADR0_tri/SMB_ADR1_tri), which provide nine unique addresses (0x50–0x58). Each device must have distinct address settings; no software address remapping is supported.

Does the PI6CG330440 support daisy-chained SBI configuration?

Yes. The SBI interface supports both star and daisy-chain topologies. In daisy chain, SBI_OUT of one device connects to SBI_IN of the next, requiring 20 bits per device shifted sequentially - e.g., 40 bits for two devices. SHFT_LD# remains device-local; only SBI_CLK and SBI_IN are shared.