Diodes Incorporated PI6CG33201CZDIEX

Overview

PI6CG33201CZDIEX from Diodes Incorporated is a 3.3V, 2-output PCIe clock generator with integrated HCSL drivers, on-chip 100Ω termination, and spread-spectrum control. It accepts a 25MHz crystal or CMOS reference input and delivers two 100MHz differential HCSL clocks compliant with PCIe Gen1–Gen6. Used in server motherboard clock trees for CPU/PCIe slot timing distribution.

For engineers reviewing the PI6CG33201CZDIEX datasheet, PI6CG33201CZDIEX pinout, PI6CG33201CZDIEX application, or PI6CG33201CZDIEX equivalent, key selection criteria include differential output jitter (<50ps cycle-to-cycle), programmable slew rate per output, individual OE# control, REFOUT phase jitter (<0.3ps RMS, SSC off), and SMBus-configurable spread-spectrum options (0%, –0.25%, –0.5%).

Technical Context

This device implements a proprietary low-jitter PLL architecture optimized for PCIe common-clock and SRIS architectures, supporting both 12kHz–5MHz integrated phase jitter measurement bands. It operates in two primary modes: crystal oscillator mode (25MHz fundamental) and CMOS reference mode, with internal 8pF load capacitance and 50Ω ESR support.

Configuration is handled via strapping pins (SADR, SS_SEL_TRI, OE#, PD#) or SMBus interface (7-bit address 0x68/0x6A), enabling dynamic control of output amplitude (0.6V–0.85V), slew rate (2.2–4.0 V/ns), and spread-spectrum modulation (30–33kHz triangular). Outputs remain blocked until PLL lock detection completes.

Key Specifications

Pinout & Package

Package: 24-lead 4×4mm TQFN (exposed pad), RoHS-compliant, halogen- and antimony-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generation applications.

Compared with ICS843002AGILFT and Si53320-B-GM, PI6CG33201CZDIEX uniquely integrates on-chip HCSL termination, per-output SMBus-programmable amplitude/slew rate, and a low-jitter REFOUT-enabling smaller footprint, lower EMI, and greater flexibility in PCIe Gen1–Gen6 timing designs without external component trade-offs.

Availability

PI6CG33201CZDIEX is available at Aetrix Electronics and suitable for server motherboard design, PCIe Gen5 add-in card development, and enterprise storage controller timing requiring stable component supply and full PCIe Gen1–Gen6 compliance.

Supply support for PI6CG33201CZDIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance timing, power management, and signal integrity solutions for industrial, computing, and communications markets.

The PI6CG33201C product line delivers ultra-low-jitter PCIe clock generators optimized for next-generation server, storage, and networking platforms where signal integrity, power efficiency, and layout simplicity are critical.

FAQ

What is the default SMBus address for PI6CG33201CZDIEX, and how is it set?

The default SMBus address is 0x68 (read) or 0x69 (write) when SADR is pulled low, and 0x6A (read) or 0x6B (write) when SADR is pulled high. The address is latched on the first rising edge of PD# after power-up and cannot be changed dynamically. SADR has an internal pull-down, so 0x68/0x69 is the factory-default configuration unless externally strapped.

Does PI6CG33201CZDIEX support both crystal and CMOS reference inputs simultaneously?

No. XTAL_IN/CLK accepts either a 25MHz fundamental-mode crystal (with internal 8pF load capacitance) or a CMOS-level 25MHz clock signal-not both. The device automatically detects oscillation presence but does not switch between input types dynamically. Crystal mode requires connection to both XTAL_IN/CLK and XTAL_OUT; CMOS mode uses XTAL_IN/CLK only.

How does the on-chip termination affect PCB layout and signal integrity?

The integrated 100Ω differential termination eliminates eight external 50Ω resistors (four per HCSL pair), reducing component count, board area, and stub-induced reflections. It maintains consistent impedance matching directly at the driver output, improving rise/fall time symmetry and reducing deterministic jitter caused by mismatched external terminations-especially beneficial in high-density server backplanes.

Can spread spectrum be enabled or disabled after power-up using SMBus commands?

No. Spread-spectrum mode is latched at power-up via the SS_SEL_TRI pin (0/M/1). SMBus bits B1[4:3] can adjust the spread amount (–0.25% or –0.5%) only if B1[5] = 1 and spread was initially enabled in hardware. Attempting to toggle spread on/off via SMBus requires a full power cycle; dynamic enable/disable is not supported.