Diodes Incorporated PI6CG33202CZDIEX

Overview

PI6CG33202CZDIEX from Diodes Incorporated is a 3.3V, 2-output PCIe clock generator with on-chip HCSL termination, supporting 25MHz crystal/CMOS input and generating 100MHz differential outputs compliant with PCIe Gen1–Gen6. It features individual output enable, programmable slew rate/amplitude per output, selectable spread-spectrum (0%, −0.25%, −0.5%), and <50ps differential cycle-to-cycle jitter. Used in high-speed server motherboard clock trees.

For engineers reviewing the PI6CG33202CZDIEX datasheet, PI6CG33202CZDIEX pinout, PI6CG33202CZDIEX application, or PI6CG33202CZDIEX equivalent, key selection criteria include PCIe Gen6 phase jitter compliance (<0.1ps RMS), integrated 85Ω HCSL termination eliminating eight external resistors, dual independent OE# control, REFOUT CMOS reference output with <0.3ps RMS phase jitter (SSC off), and SMBus-configurable output amplitude/slew rate.

Technical Context

The PI6CG33202CZDIEX employs a proprietary PLL architecture optimized for PCIe common-clock and SRIS architectures, with configurable PLL bandwidth (2–5MHz) and CDR lock frequency (10MHz). Its dual-output structure supports independent enable/disable via OE0# and OE1#, and differential skew is maintained below 50ps across temperature and voltage.

Configuration is supported via strapping pins (SADR, SS_SEL_TRI, PD#) and SMBus interface (7-bit address, block read/write), enabling dynamic adjustment of spread-spectrum depth, output amplitude (0.6V–0.85V), slew rate (0.9–4V/ns), and REFOUT characteristics without hardware change.

Key Specifications

Pinout & Package

PI6CG33202CZDIEX is housed in a 24-lead, 4×4 mm TQFN package with exposed thermal pad (Epad), RoHS-compliant and halogen-free. Pin functions are validated per Diodes DS42292 Rev 4-2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with ICS843002AGI-01LFT and Si53320-A01A-GM, PI6CG33202CZDIEX uniquely combines PCIe Gen6 phase jitter compliance, dual HCSL outputs with on-chip 85Ω termination, and SMBus-configurable amplitude/slew rate-enabling lower BOM cost, reduced layout risk, and field-tunable signal integrity in high-density server and storage platforms.

Availability

PI6CG33202CZDIEX is available at Aetrix Electronics and suitable for server motherboard clock trees, PCIe switch timing modules, enterprise SSD controller boards, and high-density NVMe storage enclosures requiring stable component supply across multi-year production cycles.

Supply support for PI6CG33202CZDIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs, with design centers in Asia, Europe, and the US, and manufacturing in ISO/TS 16949-certified facilities.

The PI6CG33202CZDIEX belongs to Diodes' PCIe-optimized clock generator product line, engineered specifically for low-jitter, low-power, high-reliability timing in next-generation data center infrastructure-including Gen6-capable servers, AI accelerators, and ultra-dense storage systems.

FAQ

What is the default SMBus address for PI6CG33202CZDIEX, and how is it set?

The default SMBus address is determined by the SADR pin state at first PD# high assertion: logic low selects 0x68 (1101000b), logic high selects 0x6A (1101010b). This address is latched and remains fixed until next power cycle. The device operates as SMBus slave only and supports block read/write protocols with no address arbitration.

Does PI6CG33202CZDIEX support both common-clock and SRIS PCIe architectures?

Yes. It meets jitter specifications for both PCIe Common Clock (CC) and Separate Reference Independent Spread (SRIS) architectures: phase jitter is <0.1ps RMS (12kHz–5MHz) for Gen6 CC and <0.05ps RMS for Gen6 SRIS. PLL bandwidth is configurable via SMBus to match required CDR loop dynamics in either architecture.

How does the on-chip 85Ω termination reduce design risk compared to discrete termination?

On-chip 85Ω termination eliminates eight external surface-mount resistors per device, removing placement tolerance errors, solder joint reliability concerns, and parasitic inductance from resistor pads. It guarantees matched impedance across temperature (±10%) and voltage (3.135–3.465 V), improving HCSL signal fidelity on long traces and reducing pre-layout simulation uncertainty.

Can PI6CG33202CZDIEX operate with an external 25 MHz CMOS clock instead of a crystal?

Yes. XTAL_IN/CLK accepts either a 25 MHz fundamental-mode crystal (with internal 8 pF load capacitance) or a CMOS-level 25 MHz square wave. When using external CMOS input, XTAL_OUT is disabled and must be left unconnected. Input rise/fall times are specified ≤5 ns, and VIH/VIL thresholds follow standard 3.3V LVCMOS levels.