Diodes Incorporated PI6CG332Q2ZDWEX

Overview

PI6CG332Q2ZDWEX from Diodes Incorporated is a 2-output PCIe Gen 6-compliant clock generator for automotive applications, accepting a 25MHz crystal or CMOS input to produce two 100MHz low-power HCSL differential clock outputs with on-chip 85Ω/100Ω termination, integrated spread-spectrum control (0%, –0.25%, or –0.5%), and a buffered CMOS reference output. It operates at 3.3V supply and meets AEC-Q100 Grade 2 (–40°C to +105°C).

For engineers reviewing the PI6CG332Q2ZDWEX datasheet, PI6CG332Q2ZDWEX pinout, PI6CG332Q2ZDWEX application, or PI6CG332Q2ZDWEX equivalent, key selection criteria include PCIe 6.0 common-clock jitter compliance (<0.04ps RMS), differential output-to-output skew <50ps, individual output enable (OE0#/OE1#), SMBus programmability of slew rate/amplitude, and automotive qualification with PPAP capability.

Technical Context

The PI6CG332Q2ZDWEX implements a proprietary analog PLL architecture optimized for ultra-low phase jitter in PCIe 6.0 common-clock mode, with integrated loop filtering and digitally assisted calibration. Its dual HCSL outputs are independently enabled and feature programmable amplitude (0.6V–0.85V) and slew rate (2.2–4.0 V/ns), while the REFOUT provides a low-noise 100MHz CMOS clock with configurable slew (0.9–3.2 V/ns).

Differential outputs remain blocked until PLL lock detection completes, ensuring glitch-free startup. Spread-spectrum modulation (30–33kHz triangular) is selectable via hardware strapping (SS_SEL_TRI) or SMBus, and power management includes dedicated PD# pin for hardware-initiated power-down with wake-on-LAN support via REFOUT control.

Key Specifications

Pinout & Package

PI6CG332Q2ZDWEX is housed in a 24-contact, 4mm × 4mm ZDW (Wettable Flank QFN) package with exposed thermal pad (EPAD) connected to GND. The package supports automated optical inspection (AOI) and provides enhanced thermal dissipation for automotive under-hood environments.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generation applications.

Compared with Si5341-A01AGM and ICS843002AGILFT, the PI6CG332Q2ZDWEX uniquely balances PCIe Gen 6 readiness, automotive qualification, on-chip termination, and hardware-strappable spread spectrum-making it optimal for next-generation automotive compute and Gen 6 storage where reliability, EMI control, and layout simplicity are co-prioritized.

Availability

PI6CG332Q2ZDWEX is available at Aetrix Electronics and suitable for automotive ADAS domain controllers, PCIe Gen 6 SSD add-in cards, and industrial backplane systems requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant sourcing.

Supply support for PI6CG332Q2ZDWEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs, with leadership in precision timing, power management, and automotive-qualified components.

The PI6CG332Q2ZDWEX belongs to Diodes' PCIe clock generator product line, engineered specifically for high-reliability automotive and datacenter applications demanding Gen 6–compliant jitter performance, spread-spectrum EMI reduction, and AEC-Q100 qualification.

FAQ

What is the function of the SS_SEL_TRI pin?

The SS_SEL_TRI pin is a tri-level latched input that sets the initial spread-spectrum amount (0%, –0.25%, or –0.5%) at power-up before SMBus communication begins. It features internal pull-up and pull-down resistors for robust noise immunity in automotive harnesses and avoids reliance on software initialization for EMI control.

Does PI6CG332Q2ZDWEX require external termination resistors for HCSL outputs?

No. The device integrates programmable on-chip 85Ω or 100Ω termination for both HCSL output pairs (Q0 and Q1), eliminating the need for eight external resistors. This reduces PCB area, simplifies layout, improves signal integrity consistency, and removes trace impedance matching dependencies.

How does the PD# pin interact with SMBus-controlled output enable?

The PD# pin provides hardware-level power-down control that overrides SMBus-configured output states. When PD# is asserted low, all differential outputs enter Hi-Z and REFOUT is disabled (unless Wake-on-LAN is enabled via Byte 3 bit 5). SMBus registers retain their values, allowing immediate resumption of prior configuration upon PD# de-assertion.

Can the REFOUT be used as a standalone clock source independent of the HCSL outputs?

Yes. REFOUT operates as an independent, buffered 100MHz LVCMOS clock with configurable slew rate (0.9–3.2 V/ns) and output enable (via SMBus Byte 3 bit 4 or hardware OE logic). It remains functional even when both Q0 and Q1 outputs are disabled, making it suitable for feeding auxiliary logic, microcontrollers, or ADCs without affecting PCIe timing paths.