Diodes Incorporated PI6CG33401CZHIEX

Overview

PI6CG33401CZHIEX from Diodes Incorporated is a 3.3V, 4-output PCIe clock generator with on-chip HCSL termination, 25MHz crystal/CMOS input, 100MHz differential outputs, <50ps cycle-to-cycle jitter, and PCIe Gen1–Gen6 compliance. It serves as a system timing hub in high-speed server and storage platforms requiring low-power, low-jitter clock distribution.

For engineers reviewing the PI6CG33401CZHIEX datasheet, PI6CG33401CZHIEX pinout, PI6CG33401CZHIEX application, or PI6CG33401CZHIEX equivalent, key selection criteria include differential output skew (<50ps), programmable slew rate per output, spread-spectrum control (0% / –0.25% / –0.5%), individual OE# enable logic, and integrated 100Ω on-die termination eliminating 16 external resistors.

Technical Context

The PI6CG33401CZHIEX employs a proprietary PLL architecture optimized for PCIe common-clock and SRIS architectures, with configurable loop bandwidth (2–5MHz) and CDR reference at 10MHz. It supports both crystal (25MHz fundamental mode, 8pF load) and CMOS reference inputs, and delivers four independent HCSL outputs with per-channel amplitude (0.6–0.85V) and slew rate (0.9–4V/ns) control via SMBus.

Power management includes hardware PD#-controlled power-down mode (IDD_PD ≤2mA), Wake-on-LAN mode (IDDA_WL ≤1mA), and tri-level SS_SEL_TRI pin for initial spread-spectrum selection. All outputs remain blocked until PLL lock detection, and REFOUT provides a buffered LVCMOS reference with <0.3ps RMS phase jitter (SSC off).

Key Specifications

Pinout & Package

Package: 32-lead, 5mm × 5mm TQFN with exposed thermal pad (EPAD). RoHS-compliant, halogen- and antimony-free "Green" construction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with IDT8T49N242A and Si5332A-D05784-GM, the PI6CG33401CZHIEX uniquely combines PCIe Gen1–Gen6 compliance, integrated 100Ω HCSL termination, tri-level hardware SSC selection, and per-output SMBus programmability in a compact 5mm × 5mm TQFN - delivering lowest BOM count and fastest bring-up for Gen5/Gen6 server and AI accelerator designs.

Availability

PI6CG33401CZHIEX is available at Aetrix Electronics and suitable for PCIe Gen5 server backplanes, AI accelerator cards, enterprise NVMe SSD controllers, and 5G fronthaul modules requiring stable component supply, long-term lifecycle support, and RoHS/Green compliance.

Supply support for PI6CG33401CZHIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, communications, and industrial markets.

The PI6CG33401CZHIEX belongs to Diodes' PCIe-optimized clock generator product line, designed specifically to address Gen5/Gen6 timing challenges in data center servers, AI accelerators, and high-speed storage systems with ultra-low jitter, integrated termination, and flexible power management.

FAQ

What is the default output impedance and how is it implemented?

The PI6CG33401CZHIEX defaults to 100Ω differential output impedance (ZOUT) per HCSL pair, achieved through on-die termination circuitry. This eliminates the need for 16 external 50Ω resistors typically required for HCSL termination, reducing PCB area, BOM cost, and signal integrity risk from layout asymmetry. The 100Ω value is fixed and not software-configurable.

How does the SS_SEL_TRI pin interact with SMBus spread-spectrum control?

The SS_SEL_TRI pin is a tri-level hardware latch that sets the initial spread-spectrum amount (0%, –0.25%, or –0.5%) at power-up before SMBus communication begins. Once latched, SMBus bits B1[4:3] can adjust the spread amount only if B1[5] = 1; however, turning SSC ON/OFF via SMBus after power-up requires a full device reset. The hardware pin ensures deterministic SSC behavior in unconfigured systems.

Can REFOUT operate independently of the HCSL outputs?

Yes. REFOUT is a buffered LVCMOS 100MHz output powered by VDD_REFOUT and controlled independently via SMBus Byte 3 (bits 4 and 5). It remains functional even when all HCSL outputs are disabled via OE# pins or SMBus register control. In power-down mode (PD# = low), REFOUT is disabled unless Wake-on-LAN mode is enabled (Byte 3 bit 5 = 1), allowing selective clock retention.

What is the minimum assertion time for PD# to enter power-down mode?

The PD# pin must be held low for ≥100ns to reliably enter power-down mode, per Diodes' characterization. During this transition, all HCSL outputs go to high-impedance state within 1 clock cycle, and total supply current drops to ≤2mA (IDD_PD). Deassertion (PD# high) requires 20–300µs for full output re-enablement (tPDLAT), including PLL relock and output stabilization.