Diodes Incorporated PI6CG33401ZHIEX

Overview

PI6CG33401ZHIEX from Diodes Incorporated is a 3.3V, 4-output PCIe Gen1–Gen5 clock generator with on-chip HCSL termination, 25MHz crystal/CMOS input, 100MHz differential outputs, <50ps cycle-to-cycle jitter, and SMBus programmability. It serves as a low-power timing source in server motherboard clock trees, replacing external termination resistors and reducing layout complexity.

For engineers reviewing the PI6CG33401ZHIEX datasheet, PI6CG33401ZHIEX pinout, PI6CG33401ZHIEX application, or PI6CG33401ZHIEX equivalent, key selection criteria include PCIe Gen5 phase jitter compliance (≤0.15ps RMS), per-output enable control (OE0#–OE3#), selectable spread-spectrum (-0.25%/-0.5%), and 32-pin 5mm × 5mm TQFN package with analog/digital power domain separation.

Technical Context

The PI6CG33401 employs a proprietary PLL architecture optimized for PCIe Gen5 (20GHz Nyquist) with integrated loop filter and 500kHz–1.8MHz bandwidth selection. Its output stage delivers four independent low-power HCSL pairs (Q0–Q3), each configurable via SMBus for slew rate (2.2–4 V/ns), amplitude (660–850 mV), and enable state.

Configuration is supported through strapping pins (SS_SEL_TRI, SADR, PD#) and SMBus (7-bit address 0x68/0x6A), enabling dynamic adjustment of spread-spectrum modulation (0%/–0.25%/–0.5%), REFOUT slew rate (1.4–3.2 V/ns), and Wake-on-LAN REFOUT behavior. Differential skew is guaranteed ≤50ps across all outputs under load.

Key Specifications

Pinout & Package

Package: 32-lead 5mm × 5mm TQFN with exposed thermal pad (EPAD). Pin pitch: 0.5mm. RoHS-compliant, halogen-free, lead-free construction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with IDT8T49N242A and Si5332A-D-GM, the PI6CG33401ZHIEX uniquely combines PCIe Gen5 phase jitter compliance, on-chip HCSL termination, and hardware-strapped spread-spectrum in a compact 5mm × 5mm TQFN-reducing component count by 16 resistors and eliminating post-power-up SMBus configuration latency.

Availability

PI6CG33401ZHIEX is available at Aetrix Electronics and suitable for server motherboard design, PCIe switch timing modules, industrial embedded controllers, and high-speed NIC development requiring stable component supply and PCIe Gen5 timing compliance.

Supply support for PI6CG33401ZHIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for power management, signal integrity, and timing applications.

The PI6CG33401 belongs to Diodes' PCIe-optimized clock generator product line, designed specifically to meet Gen1–Gen5 jitter, skew, and EMI requirements while minimizing external components and board space.

FAQ

What is the default output termination impedance of the PI6CG33401ZHIEX?

The default differential output termination impedance is 100Ω, implemented on-die for each HCSL output pair (Q0–Q3). This eliminates the need for external 50Ω series resistors per leg and ensures matched impedance without layout-dependent variations. The value is fixed and not user-programmable.

How does the PI6CG33401ZHIEX handle power-down sequencing?

Asserting PD# low places the device into hardware power-down mode, disabling all differential outputs (Q0–Q3) and reducing total supply current to ≤2mA. On first PD# high transition, the device samples strapping pins (SS_SEL_TRI, SADR) and initiates PLL lock; outputs remain blocked until lock is achieved (tSTAB ≤1ms).

Can the REFOUT pin be used simultaneously as an SMBus address selector and a clock output?

No - Pin 6 (SADR/REFOUT) operates in mutually exclusive modes. When configured as SADR (default at power-up), it latches SMBus address; when enabled via Byte 3, bit 4, it becomes a buffered 25MHz LVCMOS REFOUT. The function is selected by register write, not concurrent operation.

What is the maximum allowable crystal ESR for stable operation with the PI6CG33401ZHIEX?

The maximum recommended crystal ESR is 50Ω at 25MHz fundamental mode. Crystals exceeding this value may fail to start or exhibit unstable oscillation due to insufficient drive level margin. Diodes specifies 200µW maximum drive level and 8pF internal load capacitance for optimal matching.