Diodes Incorporated PI6CG33402CZHIEX

Overview

PI6CG33402CZHIEX from Diodes Incorporated is a 3.3V, 4-output PCIe clock generator with integrated 85Ω HCSL termination, 25MHz crystal/CMOS input, 100MHz differential outputs, and PCIe Gen1–Gen6 compliance. It delivers <50ps cycle-to-cycle jitter and supports spread-spectrum options (0%, –0.25%, –0.5%) for EMI reduction in high-speed server and storage systems.

For engineers reviewing the PI6CG33402CZHIEX datasheet, PI6CG33402CZHIEX pinout, PI6CG33402CZHIEX application, or PI6CG33402CZHIEX equivalent, key selection criteria include differential output skew (<50ps), individual OE# control per output, SMBus programmability of slew rate/amplitude, and wake-on-LAN–capable REFOUT with <0.3ps RMS phase jitter (SSC off).

Technical Context

This device implements a proprietary PLL architecture optimized for PCIe SRIS and CC timing architectures, supporting integrated phase jitter as low as 0.03ps RMS (PCIe Gen6) and meeting all PCIe Gen1–Gen6 common clock and independent reference clock jitter limits. Its analog/digital power domain separation (VDDA/VDDO/VDD_DIG) enables precise noise isolation for low-jitter clock synthesis.

The clock generator accepts a 25MHz fundamental-mode crystal or CMOS reference, generates four 100MHz HCSL outputs with on-chip 85Ω termination, and provides a buffered CMOS REFOUT with configurable slew rate (0.9–4.0 V/ns) and amplitude. Configuration is supported via strapping pins or SMBus (7-bit address, block read/write protocol), with hardware-latched SS_SEL_TRI enabling initial spread-spectrum selection.

Key Specifications

Pinout & Package

Package: 32-lead 5mm × 5mm TQFN with exposed thermal pad (EPAD) connected to GND. Pin pitch: 0.5mm. RoHS-compliant, halogen- and antimony-free "Green" construction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with ICS8430I-01T and Si53320-D-GM, PI6CG33402CZHIEX uniquely integrates on-die 85Ω HCSL termination, achieves PCIe Gen6-compliant jitter (0.03ps RMS), and supports hardware-configurable spread spectrum - delivering lower BOM cost, superior signal integrity, and faster time-to-market for Gen5/Gen6 storage and server designs.

Availability

PI6CG33402CZHIEX is available at Aetrix Electronics and suitable for enterprise SSD controller timing, PCIe switch and retimer timing, server motherboard clocking, and storage array backplane synchronization requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant green packaging.

Supply support for PI6CG33402CZHIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance timing, power management, and signal integrity solutions for computing, industrial, and automotive markets.

The PI6CG33402C product line targets PCIe Gen1–Gen6 infrastructure applications, delivering ultra-low jitter, integrated termination, and flexible configuration to simplify high-speed clock distribution in data center and storage systems.

FAQ

What is the function of the SS_SEL_TRI pin on PI6CG33402CZHIEX?

The SS_SEL_TRI pin is a tri-level latched input that sets the initial spread-spectrum amount at power-up: logic '0' selects 0% spread, 'M' (mid-voltage ≈0.5×VDD) disables spread, and '1' enables –0.5% spread. It uses internal pull-up and pull-down resistors for robust default configuration without external components, and its state is sampled only once during first PD# assertion.

Can PI6CG33402CZHIEX operate with an external 25MHz CMOS clock instead of a crystal?

Yes - Pin 2 (XTAL_IN/CLK) accepts either a 25MHz fundamental-mode crystal (with internal 8pF load capacitance) or a CMOS-level 25MHz clock signal. The device automatically detects input type and configures oscillator circuitry accordingly; no configuration register change is needed, and all jitter specifications apply equally to both input sources.

How does the wake-on-LAN mode affect REFOUT and power consumption?

In wake-on-LAN mode (PD# = low, SMBus Byte 3 bit 5 = 1), REFOUT remains active while all HCSL outputs are disabled, drawing only IDDA_WL <1mA and IDD_WL <6mA. This allows the host to monitor REFOUT for wake events without powering full clock tree, enabling rapid system resume with sub-millisecond latency and minimal standby current.

What is the maximum allowable trace length for HCSL outputs without external termination?

The HCSL outputs are designed for direct connection to PCIe receivers with 85Ω differential input impedance over trace lengths up to 5 inches (as validated in datasheet test conditions). Longer traces require careful simulation, but on-chip termination maintains signal integrity up to this length without external resistors - verified by differential output skew <50ps and cycle-to-cycle jitter <50ps at 100MHz.