Diodes Incorporated PI6CG334Q2ZHWEX

Overview

PI6CG334Q2ZHWEX from Diodes Incorporated is a 4-output PCIe Gen 6 clock generator for automotive applications, featuring 3.3V supply, 25MHz crystal/CMOS input, four differential low-power HCSL outputs with on-chip termination, and AEC-Q100 Grade 2 qualification. It delivers 100MHz outputs with <0.04ps RMS jitter (PCIe 6.0 common clock), selectable spread-spectrum (-0.25%/-0.5%), and individual output enable control for high-speed server and ADAS domain controllers.

For engineers reviewing the PI6CG334Q2ZHWEX datasheet, PI6CG334Q2ZHWEX pinout, PI6CG334Q2ZHWEX application, or PI6CG334Q2ZHWEX equivalent, key selection criteria include PCIe 6.0 jitter compliance, automotive-grade power-down/wake-on-LAN behavior, HCSL output amplitude programmability (0.6–0.85V), and SMBus-configurable slew rate per channel.

Technical Context

This device implements a proprietary PLL architecture optimized for PCIe 6.0 common-clock timing, with integrated 50Ω on-die HCSL terminations eliminating 16 external resistors. Its dual-reference capability supports both crystal (25MHz fundamental mode) and CMOS input sources, while internal analog/digital power domains (VDDA/VDDO/VDD_DIG) isolate noise-sensitive PLL circuitry from digital control logic.

Configuration is supported via strapping pins (SADR, SS_SEL_TRI, OE#) and SMBus interface (7-bit address 0x68/0x6A), enabling dynamic adjustment of output amplitude, slew rate, spread-spectrum depth, and REFOUT enable state - all without requiring reprogramming of non-volatile registers.

Key Specifications

Pinout & Package

Package: 32-contact, 5mm × 5mm WQFN (ZHW) with exposed EPAD ground connection. Thermal resistance θ_JA = 35°C/W typical.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with IDT8T49N242BILF and Si5341-A01A-GM, the PI6CG334Q2ZHWEX uniquely combines PCIe 6.0 jitter compliance, AEC-Q100 Grade 2 qualification, on-chip HCSL termination, and tri-level spread-spectrum control - making it the only drop-in solution for next-generation automotive PCIe 6.0 timing.

Availability

PI6CG334Q2ZHWEX is available at Aetrix Electronics and suitable for automotive ADAS domain controllers, PCIe 6.0 server backplanes, and industrial data acquisition systems requiring stable component supply across extended product lifecycles.

Supply support for PI6CG334Q2ZHWEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for automotive, industrial, and computing markets.

The PI6CG334Q belongs to Diodes' PCIe-optimized clock generator product line, designed specifically to meet the stringent jitter, EMI, and automotive reliability requirements of PCIe Gen 4/5/6 systems.

FAQ

What is the minimum required crystal load capacitance for PI6CG334Q2ZHWEX?

The PI6CG334Q2ZHWEX specifies an internal capacitance of 8pF on both XTAL_IN and XTAL_OUT pins. It is designed to operate with standard 25MHz fundamental-mode crystals rated for 8pF load capacitance. Using crystals with higher load capacitance (e.g., 12pF) will result in frequency deviation exceeding PCIe 6.0 ±50ppm tolerance.

How does the SS_SEL_TRI pin interact with SMBus-controlled spread spectrum?

The SS_SEL_TRI pin sets the initial spread-spectrum depth (0%, –0.25%, or –0.5%) at power-up before SMBus initialization. Once configured via SMBus (Byte 1 bits [4:3]), the hardware latch is overridden - but changing spread-spectrum state (ON/OFF) after power-up requires a full device reset, as stated in the datasheet Note 1 for Byte 1.

Can PI6CG334Q2ZHWEX drive PCIe 6.0 receivers without external AC coupling capacitors?

Yes. The PI6CG334Q2ZHWEX HCSL outputs are DC-coupled and compliant with PCIe 6.0 HCSL v1.0 specification, which defines a nominal 0.4V common-mode voltage and 800mV differential swing. Its output voltage range (VOH = 660–850mV, VOL = –150–150mV) meets receiver input thresholds without requiring AC coupling or level-shifting components.

What is the power-up sequence requirement for reliable PLL lock?

No strict power sequencing is required between VDDO, VDDA, VDD_DIG, and VDD_REFOUT - all may be ramped simultaneously within 3.135–3.465V. PLL lock occurs within 1ms after PD# deassertion and input clock stabilization, as confirmed by tSTAB = 0.75–1ms in the datasheet. External reset assertion is not needed if PD# is held low during power ramp.