Diodes Incorporated PI6CG33601CZLAIEX

Overview

PI6CG33601CZLAIEX from Diodes Incorporated is a 3.3V, 6-output PCIe clock generator with integrated HCSL drivers, on-chip 100Ω termination, and spread-spectrum capability. It accepts a 25MHz crystal or CMOS reference input and delivers six 100MHz differential low-power HCSL clocks compliant with PCIe Gen1–Gen6, plus one buffered CMOS REFOUT. Designed for server motherboard clock distribution, it eliminates 24 external termination resistors and supports per-output enable/disable and programmable slew rate.

For engineers reviewing the PI6CG33601CZLAIEX datasheet, PI6CG33601CZLAIEX pinout, PI6CG33601CZLAIEX application, or PI6CG33601CZLAIEX equivalent, this device serves as a drop-in timing solution for high-density PCIe slot fanout, requiring precise phase jitter (<0.3ps RMS REFOUT, <50ps cycle-to-cycle HCSL), individual output control, and EMI reduction via selectable -0.25% or -0.5% SSC.

Technical Context

This clock generator employs a proprietary PLL architecture optimized for PCIe common-clock and independent-reference architectures, supporting both SSC-enabled and SSC-disabled operation with configurable modulation depth (0%, –0.25%, –0.5%) and frequency (30–33kHz). Its analog PLL core achieves sub-0.5ps RMS integrated phase jitter across PCIe Gen3–Gen6 bands.

The device integrates dual-domain power management: VDDA powers the PLL/analog section (22mA typ), while separate VDDO rails supply each HCSL pair (24–30mA total), enabling independent output shutdown. Configuration occurs via SMBus (block read/write, 7-bit address) or strapping pins (SS_SEL_TRI, SADR, OE#), with latch-on-power-up behavior for hardware-defined defaults.

Key Specifications

Pinout & Package

PI6CG33601CZLAIEX is housed in a 40-lead, 5×5mm TQFN package with exposed thermal pad (pin 1 marked by dot). Pin functions are validated per Diodes DS42295 Rev 4-2, including dedicated power domains (VDDA, VDDO, VDD_REFOUT), tri-state control (OE0#–OE5#), and dual-configuration interface (SMBus + strapping).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generation applications.

Compared with ICS843002AG-01T and Si5341-A01A-GM, PI6CG33601CZLAIEX offers the lowest BOM cost via integrated termination, smallest footprint (40-TQFN), and guaranteed PCIe Gen6 jitter performance - making it optimal for space-constrained, high-volume server and AI accelerator designs where PCIe timing compliance is non-negotiable.

Availability

PI6CG33601CZLAIEX is available at Aetrix Electronics and suitable for PCIe server motherboard design, AI accelerator card development, and enterprise SSD controller integration requiring stable component supply, full RoHS 3 compliance, and long-term lifecycle support.

Supply support for PI6CG33601CZLAIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance timing, power management, and signal integrity solutions for computing, industrial, and automotive markets.

The PI6CG33601C belongs to Diodes' PCIe-optimized clock generator product line, engineered specifically for high-density, low-jitter fanout in data center and AI infrastructure - prioritizing Gen6 compliance, power efficiency, and layout simplicity.

FAQ

What is the default spread-spectrum setting at power-up?

At power-up, the SS_SEL_TRI pin determines default spread-spectrum: logic high ('1') enables –0.5% SSC, mid-level ('M') disables SSC, and logic low ('0') also disables SSC. This latched value persists until SMBus writes to Byte 1 bits [4:3], provided SSEN_SWCTR (B1[5]) is set to '1'.

Can PI6CG33601CZLAIEX operate with a 100MHz CMOS input instead of 25MHz crystal?

No. The device is designed exclusively for 25MHz fundamental-mode crystal or CMOS reference input, as confirmed by oscillator specifications (FREQ = 25MHz, ESR = 50Ω, Cload = 8pF). A 100MHz input violates the oscillator circuit's operating range and will prevent PLL lock.

How does the on-chip 100Ω termination affect PCB layout?

The integrated 100Ω differential termination eliminates the need for 24 external 50Ω resistors (12 per differential pair), reducing routing congestion near the IC, minimizing stub length, and improving impedance matching on dense server motherboards - verified by Diodes' layout guidelines in DS42295 Section 5.

Is the REFOUT output compatible with 1.8V logic interfaces?

No. REFOUT is a 3.3V CMOS output with VOH ≥0.8×VDD_REFOUT and VOL ≤0.2×VDD_REFOUT. Driving a 1.8V interface requires an external level shifter, as the output swing (typically 2.64V–3.3V) exceeds 1.8V absolute maximum ratings for most 1.8V receivers.