Diodes Incorporated PI6CG33602CZLAIEX

Overview

PI6CG33602CZLAIEX from Diodes Incorporated is a 6-output, 3.3V PCIe Gen1–Gen6 clock generator with on-chip 85Ω HCSL termination, 25MHz crystal/CMOS input, and 100MHz differential outputs. It delivers <50ps cycle-to-cycle jitter, supports SMBus configuration, and integrates spread-spectrum control (0%, –0.25%, –0.5%) for EMI reduction in high-speed server and storage systems.

For engineers reviewing the PI6CG33602CZLAIEX datasheet, PI6CG33602CZLAIEX pinout, PI6CG33602CZLAIEX application, or PI6CG33602CZLAIEX equivalent, this device serves as a low-power, pin-strappable or SMBus-programmable timing solution for PCIe root complexes, switches, and NVMe SSD controllers requiring strict jitter compliance and layout simplification via integrated termination.

Technical Context

The PI6CG33602CZLAIEX employs a proprietary PLL architecture optimized for PCIe common-clock and SRIS architectures, with configurable PLL bandwidth (2–16 MHz) and CDR reference at 10 MHz. It supports dual-mode operation: crystal oscillator mode (25 MHz fundamental) or CMOS reference input, with internal 8 pF load capacitance and 50 Ω ESR tolerance.

Its timing engine provides per-output slew rate (4 settings), amplitude (4 levels), and individual enable/disable control via either dedicated OE# pins or SMBus register B0. Differential outputs remain blocked until PLL lock detection, and REFOUT phase jitter is specified at <0.3 ps RMS (SSC off) and <1.5 ps RMS (SSC on).

Key Specifications

Pinout & Package

Package: 40-lead, 5 mm × 5 mm, 0.5 mm pitch TQFN (exposed pad), RoHS-compliant and halogen-free "Green" construction.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with Si5332A-D-GM and ICS843002AGI-01LFT, the PI6CG33602CZLAIEX uniquely combines PCIe Gen6-compliant jitter, integrated HCSL termination, and tri-level strapping-reducing layout risk and component count while maintaining full SMBus configurability for production tuning.

Availability

PI6CG33602CZLAIEX is available at Aetrix Electronics and suitable for PCIe server motherboards, NVMe storage subsystems, and AI accelerator cards requiring stable component supply, long-term lifecycle assurance, and automotive-grade change control options.

Supply support for PI6CG33602CZLAIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs, with emphasis on power management, signal integrity, and timing solutions.

The PI6CG33602CZLAIEX belongs to Diodes' PCIe-optimized clock generator product line, designed specifically for high-density, low-jitter, low-power server and storage applications demanding Gen1–Gen6 compliance and simplified layout.

FAQ

What is the default spread-spectrum setting when SS_SEL_TRI is left unconnected?

SS_SEL_TRI has internal 120 kΩ pull-up and pull-down resistors, resulting in a mid-voltage (~1.65 V) that latches as 'M' - disabling spread spectrum at power-up. This is the factory-default behavior unless externally biased to '0' or '1'. No external resistor is required for SSC-off operation.

Can the REFOUT be used simultaneously with all six HCSL outputs enabled?

Yes. REFOUT operates independently from the HCSL outputs and shares only the VDD_REFOUT supply rail. When SADR/REFOUT is configured as REFOUT (low), it delivers a buffered 3.3 V CMOS clock with <0.3 ps RMS phase jitter (SSC off), fully compatible with concurrent HCSL output operation at 100 MHz.

How does the device handle power sequencing between VDDO and other supplies?

VDDO powers the HCSL output drivers and must be ramped within ±100 ms of VDD_DIG and VDDA. Diodes specifies monotonic ramping with no reverse bias; simultaneous ramping of all 3.3 V rails (VDD, VDDO, VDDA, VDD_REFOUT, VDD_OSC) is recommended. Output drivers remain in Hi-Z until VDDO reaches 2.7 V and PLL locks.

Is SMBus communication functional during power-down mode (PD# = low)?

No. When PD# is asserted low, the device enters hardware power-down mode: all digital logic, PLL, and SMBus interface are disabled. SMBus transactions require PD# = high and stable VDD rails. Configuration must be completed before asserting PD# for sleep states.