Diodes Incorporated PI6CG336Q2ZLWEX
- Part No.:
- PI6CG336Q2ZLWEX
- Manufacturer:
- Diodes Incorporated
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
PI6CG336Q2ZLWEX.pdf
- Description:
- CLOCK GENERATOR W-QFN5050-40 T&R
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
PI6CG336Q2ZLWEX from Diodes Incorporated is a 6-output PCIe Gen 6 clock generator for automotive applications, featuring 3.3V supply, 25MHz crystal/CMOS input, six differential low-power HCSL outputs with on-chip termination, and AEC-Q100 qualification. It delivers <0.04ps RMS jitter (PCIe 6.0 common clock), <50ps cycle-to-cycle jitter, and supports selectable -0.25% or -0.5% spread-spectrum modulation.
For engineers reviewing the PI6CG336Q2ZLWEX datasheet, PI6CG336Q2ZLWEX pinout, PI6CG336Q2ZLWEX application, or PI6CG336Q2ZLWEX equivalent, key selection criteria include PCIe 6.0 jitter compliance, individual output enable control, programmable slew rate per output, and automotive-grade power-down/wake-on-LAN behavior.
Technical Context
The device integrates a proprietary PLL architecture optimized for PCIe 6.0 timing integrity, with differential outputs blocked until PLL lock detection. It accepts a 25MHz fundamental-mode crystal or CMOS reference and generates six 100MHz HCSL clocks with on-chip 85Ω termination, eliminating 32 external resistors.
Configuration is supported via tri-level strapping pin SS_SEL_TRI for initial spread-spectrum selection and SMBus interface (7-bit address 0x68/0x6A) for runtime control of output enable, slew rate, amplitude, and REFOUT behavior - including wake-on-LAN mode where REFOUT remains active during power-down.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.3V nominal (3.135–3.465V); powers analog/digital/output domains separately for noise isolation |
| Input Frequency | 25MHz crystal or CMOS reference; supports fundamental-mode oscillation only |
| Output Count & Type | 6 × differential HCSL @ 100MHz + 1 × buffered CMOS REFOUT; all HCSL outputs include on-chip 85Ω termination |
| Jitter Performance | PCIe 6.0 common clock RMS jitter <0.04ps; differential cycle-to-cycle jitter <50ps; REFOUT phase jitter <0.3ps RMS (SSC off) |
| Spread Spectrum | Selectable 0%, –0.25%, or –0.5% triangular modulation at 30–33kHz; reduces EMI without compromising timing margin |
| Output Control | Individual OE# pins (active-low) per output pair; SMBus register override available for Q0–Q5 enable state |
| Automotive Qualification | AEC-Q100 Grade 2 (–40°C to +105°C ambient); PPAP-capable; manufactured in IATF 16949 certified facilities |
Pinout & Package
Package: 40-contact, 5×5mm QFN (ZLW), exposed thermal pad, RoHS-compliant and halogen-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XTAL_IN/CLK (Pin 2) | Clock Reference Input | Accepts 25MHz crystal or CMOS signal; internal 8pF capacitance; supports fundamental-mode only |
| Q0+ / Q0– to Q5+ / Q5– (Pins 14–15, 18–19, 22–23, 28–29, 33–34, 36–37) | Differential HCSL Outputs | Each pair delivers 100MHz HCSL with programmable amplitude (0.6–0.85V) and slew rate (2.2–4.0 V/ns); on-chip 85Ω termination |
| OE0#–OE5# (Pins 13, 21, 24, 30, 35, 38) | Output Enable Control | Active-low CMOS inputs with internal pull-down; disable corresponding Qn+/Qn– pair independently |
| REFOUT (via SADR/REFOUT Pin 6) | Buffered CMOS Reference Output | Configurable as SMBus address latch or LVCMOS clock; 40ns period (25MHz input), 45–55% duty cycle, <1.5ps RMS phase jitter (SSC on) |
| PD# (Pin 40) | Power-Down Control | Active-low input with internal pull-up; first high assertion initiates startup; low enters power-down mode with <2mA total IDD |
| SCLK / SDATA (Pins 9–10) | SMBus Interface | 3.3V-tolerant, 500kHz max; supports block read/write; address latched on SADR pin at PD# assertion |
Key Features
| Feature | Design Value |
|---|---|
| On-chip HCSL termination | Eliminates 32 external 85Ω resistors per design, reducing BOM count and PCB layout complexity |
| Per-output programmability | Independent SMBus control of slew rate and amplitude for each of six HCSL outputs enables board-specific signal integrity tuning |
| Differential output blocking | HCSL outputs remain inactive until PLL achieves lock, preventing spurious clocking during startup |
| Wake-on-LAN REFOUT mode | REFOUT remains active during PD#-initiated power-down when Byte 3 bit 5 = 1, supporting low-power system wake functionality |
| Tri-level spread-spectrum select | SS_SEL_TRI pin (Pin 1) provides hardware-latched selection of 0%, –0.25%, or –0.5% spread at power-up without SMBus interaction |
Applications
| Automotive ADAS Domain Controller | PCIe 6.0 SSD Controller Module |
|---|---|
Use Scenario: High-bandwidth sensor fusion in Level 3+ autonomous driving systems requiring synchronized PCIe 6.0 links between radar, camera, and AI accelerator modules. IC Role / Device Role / Timing Role: Primary clock generator providing six low-jitter 100MHz HCSL clocks to PCIe 6.0 endpoints and root complexes across multiple SoCs. Use Value: Meets PCIe 6.0 common clock jitter spec (<0.04ps RMS) while enabling per-link spread-spectrum control to pass automotive EMI tests. | Use Scenario: Enterprise NVMe SSD with dual PCIe 6.0 x4 interfaces and onboard controller FPGA requiring deterministic, low-skew clock distribution. IC Role / Device Role / Timing Role: Clock source for host-side and device-side PCIe 6.0 PHYs, with independent output enables allowing dynamic lane power gating. Use Value: Differential output-to-output skew <60ps ensures inter-lane timing alignment; on-chip termination simplifies high-density routing. |
| Automotive Infotainment Head Unit | AI Accelerator PCIe Expansion Card |
Use Scenario: Centralized infotainment platform integrating GPU, DSP, and PCIe-connected modems, operating in extended temperature environments. IC Role / Device Role / Timing Role: Timing hub delivering synchronized clocks to GPU memory interface, display controller, and PCIe 5.0/6.0 modem link. Use Value: AEC-Q100 Grade 2 qualification (–40°C to +105°C) and IATF 16949 manufacturing ensure reliability in cabin-mounted electronics. | Use Scenario: Datacenter AI training card with multiple PCIe 6.0 x16 slots and FPGA-based accelerators requiring precise clock synchronization across heterogeneous compute elements. IC Role / Device Role / Timing Role: Low-jitter clock source for FPGA transceivers and memory controllers, with SMBus configurability enabling firmware-driven timing optimization. Use Value: Programmable slew rate per output allows matching trace impedance across varied PCB stackups; REFOUT serves as clean reference for ADC/DAC subsystems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PCIe clock generation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT8T49N242BILF | 8-output, supports PCIe Gen 5 only; no on-chip HCSL termination; requires external resistors; higher typical IDD (45mA vs 34mA) | Lacks PCIe Gen 6 jitter compliance and automotive qualification; not AEC-Q100 rated | Choose only if Gen 5 support suffices and external termination is acceptable |
| Si5341-A01879-GM | Programmable 10-output clock generator; uses external crystal; no native HCSL outputs (requires level-shifting); higher jitter floor (0.1ps RMS min) | Requires additional components for HCSL conversion; not pre-validated for PCIe 6.0 common clock spec | Prefer only for multi-protocol clock synthesis needs beyond PCIe-specific timing |
Compared with IDT8T49N242BILF and Si5341-A01879-GM, the PI6CG336Q2ZLWEX uniquely combines PCIe 6.0 jitter compliance, on-chip HCSL termination, AEC-Q100 qualification, and per-output programmability in a single 5×5mm package - reducing component count and validation effort for automotive and high-speed storage designs.
Availability
PI6CG336Q2ZLWEX is available at Aetrix Electronics and suitable for automotive ADAS domain controllers, PCIe 6.0 SSD controller modules, and AI accelerator expansion cards requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for PI6CG336Q2ZLWEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for automotive, industrial, and computing markets.
The PI6CG336Q belongs to Diodes' PCIe-optimized clock generator product line, designed specifically to meet stringent jitter, EMI, and automotive reliability requirements of next-generation high-speed serial interconnects.
FAQ
What is the function of the SS_SEL_TRI pin?
The SS_SEL_TRI pin (Pin 1) is a tri-level latched input that selects spread-spectrum modulation amount at initial power-up: logic '1' enables –0.5% spread, 'M' (mid-voltage) disables spread, and '0' disables spread. It has internal pull-up and pull-down resistors, and its state is sampled on the first high assertion of PD#. SMBus registers can later adjust spread amount but cannot toggle spread on/off without reset.
How does the PI6CG336Q2ZLWEX handle power-down and wake-on-LAN?
Asserting PD# low places the device in power-down mode, reducing total current to <2mA. In wake-on-LAN mode (configured via SMBus Byte 3 bit 5 = 1), the REFOUT remains active during PD#-initiated power-down, enabling downstream circuitry to monitor events. The differential outputs remain disabled unless explicitly enabled via OE# pins or SMBus register.
Can the HCSL outputs operate without external termination resistors?
Yes - the PI6CG336Q2ZLWEX integrates 85Ω on-chip termination for all six HCSL outputs, eliminating the need for 32 external resistors. This simplifies PCB layout, improves signal integrity consistency, and reduces BOM cost. External termination is not required unless custom impedance matching is needed for specific trace geometries.
What is the significance of the ZLW package designation?
ZLW denotes Diodes Incorporated's 40-pin, 5×5mm QFN package with wettable flanks and an exposed thermal pad. It supports automated optical inspection (AOI) of solder joints and provides enhanced thermal performance for automotive under-hood applications. The package is lead-free, halogen-free, and fully RoHS 3 compliant (2015/863/EU).
PI6CG336Q2ZLWEX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- -
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Type:
- Clock Generator
- PLL:
- Yes
- Input:
- CMOS, Crystal
- Output:
- HCSL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:6
- Differential - Input:Output:
- No/Yes
- Frequency - Max:
- 100MHz
- Divider/Multiplier:
- No/No
- Voltage - Supply:
- 3.135V ~ 3.465V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 40-WQFN (5x5)
PI6CG336Q2ZLWEX FAQ
1.How can I place an order for PI6CG336Q2ZLWEX through Aetrix?
Please submit a Request for Quotation (RFQ) for PI6CG336Q2ZLWEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PI6CG336Q2ZLWEX reliable?
The price and inventory of PI6CG336Q2ZLWEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6CG336Q2ZLWEX is usually 5 days.
3.What payment methods are accepted for PI6CG336Q2ZLWEX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6CG336Q2ZLWEX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PI6CG336Q2ZLWEX?
PI6CG336Q2ZLWEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PI6CG336Q2ZLWEX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PI6CG336Q2ZLWEX?
For technical support, including PI6CG336Q2ZLWEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6CG336Q2ZLWEX requirements.
6.How does Aetrix verify that PI6CG336Q2ZLWEX is sourced from the original manufacturer or authorized distributors?
All PI6CG336Q2ZLWEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6CG336Q2ZLWEX meets industry standards.
7.What is the process for return or replacement of PI6CG336Q2ZLWEX?
All PI6CG336Q2ZLWEX units undergo pre-shipment inspection (PSI). If there is an issue with PI6CG336Q2ZLWEX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PI6CG336Q2ZLWEX part is unused and in its original packaging.
Return procedure for PI6CG336Q2ZLWEX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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