Diodes Incorporated PI6CG33801CZLIEX

Overview

PI6CG33801CZLIEX from Diodes Incorporated is an 8-output, 3.3V PCIe Gen1–Gen6 clock generator with on-chip HCSL termination, 25 MHz crystal/CMOS input, 100 MHz differential outputs, and <50 ps cycle-to-cycle jitter. It serves as a low-power timing source in high-speed server and storage backplanes requiring precise, spread-spectrum-capable reference distribution.

For engineers reviewing the PI6CG33801CZLIEX datasheet, PI6CG33801CZLIEX pinout, PI6CG33801CZLIEX application, or PI6CG33801CZLIEX equivalent, key selection criteria include PCIe Gen6 phase jitter compliance (≤0.1 ps RMS), individual output enable control per Q0–Q7 pair, programmable slew rate (0.9–4 V/ns), on-die 100 Ω HCSL termination, and SMBus-configurable spread-spectrum options (0%, −0.25%, −0.5%).

Technical Context

This device implements a proprietary PLL architecture optimized for sub-0.1 ps RMS phase jitter across PCIe Gen3–Gen6 bands (12 kHz–5 MHz integration), with dual-mode operation supporting both common-clock and SRIS architectures. It accepts a 25 MHz fundamental-mode crystal or CMOS reference and synthesizes eight 100 MHz HCSL outputs with matched skew ≤60 ps.

Configuration is supported via strapping pins (SS_SEL_TRI, SADR/REFOUT, PD#) or SMBus interface (SCLK/SDATA), enabling dynamic control of output amplitude (four levels), slew rate (four settings), and spread-spectrum modulation (triangular, 30–33 kHz). Power management includes wake-on-LAN mode (IDDA_WL = 0.5–1 mA) and full power-down (IDD_PD = 1–2 mA).

Key Specifications

Pinout & Package

PI6CG33801CZLIEX is housed in a 48-lead, 6 mm × 6 mm TQFN package with exposed thermal pad (ZLIEX suffix denotes this RoHS-compliant, green, lead-free variant).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generation applications.

Compared with IDT8T49N242A and Si5332A-D-GM, PI6CG33801CZLIEX delivers PCIe Gen6-optimized jitter performance with minimal external components and lower static/dynamic power-making it the most cost- and space-efficient choice for dedicated high-density PCIe timing applications.

Availability

PI6CG33801CZLIEX is available at Aetrix Electronics and suitable for PCIe Gen6 server backplanes, enterprise NVMe storage controllers, AI accelerator cards, and high-density FPGA mezzanine modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.

Supply support for PI6CG33801CZLIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for industrial, computing, and communications markets.

The PI6CG33801C product line delivers ultra-low-jitter, highly integrated clock generators optimized specifically for PCIe Gen1–Gen6 infrastructure-reducing design risk, layout effort, and total system cost in high-speed data center applications.

FAQ

What is the function of the SS_SEL_TRI pin?

The SS_SEL_TRI pin is a tri-level latched input that selects spread-spectrum modulation amount at power-up: logic '1' enables −0.5% spread, 'M' (mid-voltage ≈0.5×VDD) disables spread, and '0' disables spread. Its internal pull-up and pull-down resistors (120 kΩ each) ensure deterministic boot behavior without external biasing.

Does PI6CG33801CZLIEX support PCIe Gen6 Common Clock Architecture?

Yes-it meets PCIe Gen6 CCA jitter requirements with integrated phase jitter ≤0.1 ps RMS (12 kHz–5 MHz) when SSC is disabled, and ≤0.04 ps RMS in SRIS mode. The device's PLL bandwidth (2–5 MHz) and CDR lock range (10 MHz) are explicitly validated per PCI-SIG ECN specifications for Gen6 timing compliance.

How is output enable controlled-by pin or SMBus?

Both methods are supported: OE0#–OE7# pins provide hardware-level per-output enable/disable with internal pull-downs, while SMBus Byte 0 register allows software override-even forcing outputs into low/high-impedance states regardless of pin state. This dual-control scheme enables flexible power sequencing and dynamic reconfiguration.

What is the maximum allowable load capacitance on XTAL_IN/CLK?

The internal oscillator circuit is designed for 8 pF load capacitance on XTAL_IN/CLK, with guaranteed operation over ±2 pF tolerance. Exceeding 10 pF may cause startup failure or frequency drift beyond ±50 ppm; Diodes recommends using fundamental-mode 25 MHz crystals with ESR ≤50 Ω and drive level ≤200 µW for reliable operation.