Diodes Incorporated PI6CG33802CZLIEX

Overview

PI6CG33802CZLIEX from Diodes Incorporated is a 3.3V, 8-output PCIe Gen1–Gen6 clock generator with on-chip HCSL termination, 25 MHz crystal/CMOS input, and 100 MHz differential outputs. It delivers <50 ps cycle-to-cycle jitter, supports spread-spectrum (0%, –0.25%, –0.5%), and integrates a buffered CMOS REFOUT for system reference distribution in high-speed server and storage platforms.

For engineers reviewing the PI6CG33802CZLIEX datasheet, PI6CG33802CZLIEX pinout, PI6CG33802CZLIEX application, or PI6CG33802CZLIEX equivalent, key selection criteria include PCIe Gen6 phase jitter compliance (<0.1 ps RMS), per-output enable control (OE[7:0]#), SMBus programmability of slew rate and amplitude, and 48-pin TQFN package compatibility with dense PCB layouts.

Technical Context

The PI6CG33802CZLIEX employs a proprietary low-jitter PLL architecture optimized for PCIe common-clock and SRIS topologies, with configurable PLL bandwidth (2–16 MHz) and CDR lock at 10 MHz. Its dual-mode input accepts either a 25 MHz fundamental-mode crystal (8 pF load, 50 Ω ESR) or CMOS clock, enabling flexible board-level timing source integration.

All eight HCSL outputs feature on-die 85 Ω termination, eliminating 32 external resistors, while individual OE# pins and SMBus-controlled output states support dynamic power gating. The device supports wake-on-LAN mode with sub-1 mA analog supply current and enters hardware-triggered power-down (PD#) with <0.1 mA output current.

Key Specifications

Pinout & Package

Package: 48-lead, 6 mm × 6 mm, 0.5 mm pitch TQFN (exposed pad), RoHS-compliant and halogen-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generation applications.

Compared with IDT8T49N242A and Si5341-B-GM, the PI6CG33802CZLIEX uniquely combines PCIe Gen6 compliance, on-die HCSL termination, and hardware-configurable spread spectrum-enabling lower system cost, smaller footprint, and guaranteed EMI reduction without firmware dependency.

Availability

PI6CG33802CZLIEX is available at Aetrix Electronics and suitable for PCIe Gen6 server motherboards, enterprise NVMe SSDs, AI accelerator cards, and 5G baseband units requiring stable component supply across multi-year production cycles.

Supply support for PI6CG33802CZLIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for power management, signal integrity, and timing solutions.

The PI6CG33802CZLIEX belongs to Diodes' PCIe-optimized clock generator product line, designed specifically to meet stringent Gen1–Gen6 jitter, skew, and EMI requirements in high-bandwidth computing and communications infrastructure.

FAQ

What is the minimum required crystal ESR for stable operation?

The PI6CG33802CZLIEX requires a 25 MHz fundamental-mode crystal with ESR ≤50 Ω, as specified in the datasheet's crystal characteristics table. Crystals exceeding this ESR may cause startup failure or increased jitter due to insufficient drive level margin. Diodes recommends using crystals qualified per JEDEC JESD22-A108 with 8 pF load capacitance and 200 µW drive level.

How does the SS_SEL_TRI pin interact with SMBus spread-spectrum control?

The SS_SEL_TRI pin sets the initial spread-spectrum configuration at power-up and is latched on the first rising edge of PD#. Subsequent SMBus writes to Byte 1 bits [4:3] override this setting only if SSEN_SWCTR (Byte 1 bit 5) is set to '1'. If SSEN_SWCTR = '0', the hardware strap remains authoritative, ensuring deterministic EMI behavior during boot before firmware initialization.

Can the REFOUT be used simultaneously with all eight HCSL outputs enabled?

Yes-the REFOUT operates independently from the HCSL outputs and shares no current path with them. With VDD_REFOUT = 3.3 V, REFOUT delivers a buffered 25 MHz (×4 = 100 MHz) LVCMOS signal with <0.3 ps RMS phase jitter (SSC off) and 20 Ω output impedance. It remains active even when all OE# pins are asserted, supporting concurrent use as a system reference for non-PCIe peripherals.

What is the maximum allowable trace length for HCSL outputs without external termination?

The PI6CG33802CZLIEX supports up to 5-inch PCB traces for each HCSL output pair when using the default 85 Ω on-chip termination, as validated in the datasheet's "HCSL Output Characteristics" section. Longer traces require external series or parallel termination to maintain signal integrity, especially in Gen6 applications where inter-symbol interference must stay below 10% of unit interval.