Diodes Incorporated PI6CG338Q2ZLWEX

Overview

PI6CG338Q2ZLWEX from Diodes Incorporated is an 8-output PCIe Gen 6-compliant clock generator for automotive applications, featuring a 25 MHz crystal/CMOS input, 100 MHz differential Low Power HCSL outputs with on-chip 50 Ω termination, <0.04 ps RMS jitter (PCIe 6.0 common clock), and AEC-Q100 Grade 2 qualification. It integrates a proprietary PLL, individual output enable (OE[7:0]#), and SMBus programmability for slew rate and amplitude per output.

For engineers reviewing the PI6CG338Q2ZLWEX datasheet, PI6CG338Q2ZLWEX pinout, PI6CG338Q2ZLWEX application, or PI6CG338Q2ZLWEX equivalent, key selection considerations include PCIe 6.0 jitter compliance, automotive-grade power-down behavior (PD#), spread-spectrum control (SS_SEL_TRI), and HCSL output-to-output skew <60 ps in IATF 16949-manufactured devices.

Technical Context

The PI6CG338Q2ZLWEX employs a fully integrated PLL architecture optimized for PCIe Gen 6 timing integrity, locking to a 25 MHz fundamental-mode crystal or CMOS reference and generating eight synchronized 100 MHz differential HCSL clocks. Its analog PLL core achieves sub-0.04 ps RMS phase jitter under PCIe 6.0 common clock specifications.

Configuration is supported via dual-path control: strapping pins (SS_SEL_TRI, SADR, PD#) set boot-time defaults including spread-spectrum depth (0%, –0.25%, –0.5%) and SMBus address, while SMBus registers (Byte 0–3) allow runtime adjustment of output enable states, slew rates (4 settings per Qn), amplitudes (0.6–0.85 V), and REFOUT parameters.

Key Specifications

Pinout & Package

PI6CG338Q2ZLWEX is housed in a 48-contact, 6×6 mm QFN package (ZLW suffix), with exposed thermal pad, lead-free and halogen-free construction per RoHS 3 and IATF 16949 requirements.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with IDT8T49N242A and Si5341-A01A-GM, the PI6CG338Q2ZLWEX delivers Gen 6 readiness, automotive qualification, and integrated termination in a compact 6×6 mm ZLW package - making it optimal for cost-sensitive, safety-critical PCIe 6.0 automotive deployments where design simplicity and supply chain assurance are prioritized.

Availability

PI6CG338Q2ZLWEX is available at Aetrix Electronics and suitable for ADAS domain controllers, automotive PCIe 6.0 SSD interfaces, and zonal architecture backplanes requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant sourcing.

Supply support for PI6CG338Q2ZLWEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance timing, power management, and signal integrity solutions for automotive, industrial, and computing markets.

The PI6CG338Q2ZLWEX belongs to Diodes' PCIe Gen 6 clock generator product line, designed specifically to meet stringent automotive timing requirements-including AEC-Q100 Grade 2 operation, IATF 16949 manufacturing, and PCIe 6.0 jitter compliance-while reducing system-level complexity through on-chip termination and dual-mode configuration.

FAQ

What is the function of the SS_SEL_TRI pin on PI6CG338Q2ZLWEX?

The SS_SEL_TRI pin is a tri-level latched input that selects the initial spread-spectrum depth at power-up: logic high ('1') enables –0.5% spread, mid-level ('M') disables spread, and logic low ('0') disables spread. It features internal pull-up and pull-down resistors, eliminating external bias components. This setting is latched before SMBus communication begins and can be overridden later via SMBus Byte 1 bits [4:3] if SSEN_SWCTR is enabled.

How does the PI6CG338Q2ZLWEX achieve PCIe Gen 6 jitter compliance?

The PI6CG338Q2ZLWEX achieves PCIe Gen 6 jitter compliance using a proprietary analog PLL architecture optimized for ultra-low phase noise, delivering <0.04 ps RMS integrated phase jitter (12 kHz–5 MHz) and <50 ps cycle-to-cycle jitter. Its differential HCSL outputs feature tightly matched slew rates and on-die termination, minimizing skew and reflections that contribute to jitter accumulation in high-speed traces.

Can the REFOUT pin be used simultaneously with the differential outputs?

Yes, the REFOUT pin (multiplexed with SADR) can operate concurrently with the eight differential HCSL outputs. When configured as REFOUT, it provides a buffered LVCMOS 100 MHz clock with programmable slew rate (via SMBus Byte 3) and independent enable control (Byte 3 bit 4). Its dedicated VDD_REFOUT and GND_REFOUT pins ensure low-noise operation without interfering with differential output power domains.

What is the power-down behavior of PI6CG338Q2ZLWEX when PD# is asserted?

When PD# is driven low, the PI6CG338Q2ZLWEX enters hardware power-down mode: all differential outputs (Q0–Q7) go Hi-Z, REFOUT is disabled unless Wake-on-LAN is enabled (Byte 3 bit 5 = 1), and total supply current drops to ≤2 mA (IDD_PD). De-asserting PD# initiates a 25–300 µs startup latency before outputs resume, with PLL lock re-established prior to clock delivery.