Diodes Incorporated PI6CV857BAE

Overview

PI6CV857BAE from Pericom Semiconductor is a 1:10 PLL clock driver IC designed for registered DDR SDRAM memory modules. It distributes one differential SSTL-2 clock input pair (CLK, CLK) to ten matched differential SSTL-2 output pairs (Y0–Y9) and one feedback pair (FBOUT, FBOUT), operating at 2.5 V AVDD and 2.5 V VDDQ with up to 200 MHz application frequency, low skew (<50 ps), and spread-spectrum clocking support for EMI reduction in RDIMM systems.

For engineers reviewing the PI6CV857BAE datasheet, PI6CV857BAE pinout, PI6CV857BAE application, or PI6CV857BAE equivalent, this device is selected for high-precision, low-jitter clock distribution in DDR2-registered DIMM subsystems where phase alignment, output enable control via PWRDWN, and external feedback synchronization are required.

Technical Context

The PI6CV857BAE implements a PLL-based zero-delay architecture that locks to the differential reference clock (CLK/CLK) and external feedback signal (FBIN/FBIN) to maintain tight phase alignment across all ten outputs. Its internal PLL operates with 2.5 V analog core supply (AVDD) and 2.5 V I/O drivers (VDDQ), enabling SSTL-2 compliance and sub-100 ps cycle-to-cycle jitter performance.

It integrates frequency detection logic that triggers automatic power-down when input clock frequency drops below 20 MHz, disabling receivers and placing outputs in high-impedance state. The PWRDWN pin provides synchronous LVCMOS-level control over this mode, while strapping AVDD low bypasses the PLL for test-mode operation.

Key Specifications

Pinout & Package

PI6CV857BAE is housed in a Pb-free, RoHS-compliant 48-pin TSSOP package (package code A), measuring 12.6 mm × 6.2 mm × 1.2 mm, with 0.5 mm pitch and standard JEDEC MO-153 footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PLL clock buffer applications.

Compared with IDT72V2231L and NB3N502DG, the PI6CV857BAE uniquely delivers zero-delay, SSTL-2–compliant 10-output fanout with spread-spectrum tracking and automatic low-frequency power-down-making it the sole fit for production PC2700 RDIMMs requiring full specification compliance.

Availability

PI6CV857BAE is available at Aetrix Electronics and suitable for DDR2 registered DIMM manufacturing, server memory module design, and industrial embedded DDR2 systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for PI6CV857BAE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor Corporation was a fabless provider of high-performance timing, interface, and signal integrity solutions, acquired by Diodes Incorporated in 2017. Its products targeted enterprise computing, communications, and memory infrastructure.

The PI6CV857BAE belongs to Pericom's DDR clock buffer product line, engineered specifically for registered DIMM clock distribution with zero-delay PLLs, SSTL-2 I/O, and EMI-reduction features aligned to Intel PC100/PC2700 specifications.

FAQ

What is the minimum input clock frequency that prevents automatic power-down?

The PI6CV857BAE enters automatic power-down when the CLK/CLK input frequency falls below 20 MHz. This threshold is fixed and not user-adjustable. Operation above 20 MHz maintains normal PLL lock and output drive; below this, all outputs go high-impedance and internal circuitry powers down regardless of PWRDWN state.

Can FBIN/FBIN be left unconnected if FBOUT/FBOUT is not used?

No. FBIN/FBIN must be connected to FBOUT/FBOUT to close the PLL feedback loop. Leaving FBIN/FBIN floating or unconnected causes loss of lock, excessive jitter, and failure to meet timing specifications. The device requires this external feedback path for zero-delay operation and skew cancellation.

Is PI6CV857BAE compatible with DDR3 memory systems?

No. PI6CV857BAE is specified for DDR2 (SSTL-2) operation at 2.5 V and supports up to 200 MHz. DDR3 uses SSTL-15 at 1.5 V and higher frequencies (≥400 MHz). Its voltage levels, slew rates, and timing parameters do not meet DDR3 requirements, and it lacks DDR3-specific features like dynamic ODT control.

Does the device support daisy-chained feedback configurations?

No. PI6CV857BAE requires direct point-to-point connection between FBOUT/FBOUT and FBIN/FBIN. Daisy-chaining introduces additional trace delay and impedance mismatch, degrading PLL stability and increasing jitter beyond specification. The datasheet mandates a dedicated, length-matched, 60 Ω-terminated feedback path.