Diodes Incorporated PI6LC4820ZDE

Overview

PI6LC4820ZDE from Pericom Semiconductor is a low-phase-noise LC-VCO-based clock generator designed for 10GbE and multi-rate Ethernet systems. It accepts a 25 MHz crystal or 25/156.25 MHz differential input, delivers nine LVPECL/LVDS-selectable outputs at 312.5/156.25/125 MHz, and achieves ≤1 ps integrated phase jitter (12 kHz–20 MHz) with 3.3 V supply.

For engineers reviewing the PI6LC4820ZDE datasheet, PI6LC4820ZDE pinout, PI6LC4820ZDE application, or PI6LC4820ZDE equivalent, key selection criteria include bank-selectable output formats, PLL bypass mode for test, power supply noise rejection (−50 dBc @ 156.25 MHz), and independent frequency control per output bank via FS_A/B/C pins.

Technical Context

The PI6LC4820ZDE implements an LC-based VCO with programmable feedback dividers (FS1 selects ×20 or ×25), supporting three independent output banks (A, B, C) each configurable for LVPECL or LVDS via dedicated mode pins (QA_Mode0/1, QB_Mode, QC_Mode). Input selection (crystal/X1-X2, differential/IN+/IN−, or single-ended/IN_SE) is controlled by IN_SEL and PLL_BYPS.

Each bank uses integer dividers (FS_A/B/C set 125/156.25/312.5 MHz), while the crystal oscillator buffer provides a low-noise reference output. Power supply domains are segregated: VDD_PLL (PLL core), VDDA (analog), VDD_OSC (crystal), and per-bank VDD_Qx rails-enabling optimized noise isolation and jitter performance.

Key Specifications

Pinout & Package

PI6LC4820ZDE is housed in a Pb-free, green 48-lead 7×7 mm TQFN package (ZD code) with exposed thermal pad. Pin assignment follows JEDEC MO-220/VKKD standard; GND pins (7, 11, 13, 15, 17, 21, 49) provide dedicated return paths per functional domain.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Ethernet clock generator applications.

Compared with Si5338A-D-GM and ICS8430I-01T, the PI6LC4820ZDE uniquely combines triple-rate output, per-bank LVPECL/LVDS selection, and integrated crystal buffer - making it optimal for new 10GbE/25GbE infrastructure where jitter, flexibility, and integration are co-prioritized.

Availability

PI6LC4820ZDE is available at Aetrix Electronics and suitable for 10GbE line cards, multi-rate Ethernet switches, optical transport modules, and network test equipment requiring stable component supply, consistent lead times, and full traceability.

Supply support for PI6LC4820ZDE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for networking and communications infrastructure.

The PI6LC4820 belongs to Pericom's HiFlex™ Ethernet clock generator family, engineered specifically for low-jitter, multi-rate synchronization in 10GbE and emerging high-speed Ethernet systems.

FAQ

What crystal specifications are required for stable 25 MHz operation?

The PI6LC4820ZDE requires a fundamental-mode 25 MHz crystal with 18 pF load capacitance, ≤50 Ω ESR, and ±20–30 ppm stability. Recommended parts include SaRonix-eCera GC25000-76B and FL2500047. External load capacitors C1=27 pF and C2=33 pF are specified for CL=18 pF crystals; values may be tuned for board-specific parasitics.

How is LVDS vs. LVPECL output format selected per bank?

Bank C format is set by QC_Mode (pin 9); Bank A high-order outputs (QA4/QA3) use QA_Mode1 (pin 19), while QA2/QA1/QA0 use QA_Mode0 (pin 44); Bank B uses QB_Mode (pin 45). Driving these pins to VDD selects LVPECL; grounding selects LVDS; floating tri-states the bank. Each bank has its own VDD_Qx supply rail.

Can the PI6LC4820ZDE generate 312.5 MHz and 156.25 MHz simultaneously?

Yes. FS_A=1/FS_B=1/FS_C=1 configures Bank A for 125 MHz, Bank B for 156.25 MHz, and Bank C for 312.5 MHz - all active concurrently. The LC-VCO runs at 1.25 GHz (×4 × 312.5 MHz), and integer dividers distribute harmonically related outputs without added jitter from fractional synthesis.

What is the purpose of the PLL_BYPS pin and when should it be used?

PLL_BYPS (pin 6) disables the PLL and routes the selected input (crystal or differential) directly to all outputs. This mode is used during system bring-up to verify signal integrity without PLL-induced jitter, validate input path functionality, or establish a known low-jitter baseline before enabling closed-loop operation.