Diodes Incorporated PI6LC4840ZHE

Overview

PI6LC4840ZHE from Pericom Semiconductor is a crystal-to-LVDS/LVCMOS frequency synthesizer with LC-based VCO architecture, designed for high-integrity Ethernet clocking. It delivers low-phase-noise 25 MHz and 125 MHz outputs, supports pin-selectable 25/50 MHz LVCMOS (Bank A), fixed 125 MHz LVCMOS (Bank B), and 125 MHz LVDS (Bank C), and operates across –40°C to +85°C industrial temperature range.

For engineers reviewing the PI6LC4840ZHE datasheet, PI6LC4840ZHE pinout, PI6LC4840ZHE application, or PI6LC4840ZHE equivalent, key selection criteria include integrated phase jitter (≤1 ps, 12 kHz–20 MHz @125 MHz), triple-output bank configuration, 3.3 V ±5% supply tolerance, crystal input compatibility (25 MHz, 18 pF load), and TQFN-32 (ZH) package thermal and layout constraints.

Technical Context

The PI6LC4840ZHE implements an LC-VCO-based PLL architecture with programmable mode pins (Mode[2:0]) enabling per-bank output enable and frequency selection-e.g., Bank A outputs can be set to 25 MHz or 50 MHz, while Banks B and C are fixed at 125 MHz. The device integrates separate analog (VDDA) and digital (VDD) supplies, plus independent output buffer rails (VDDO_REF, VDDO_QA/B/C) for noise isolation.

It accepts a 25 MHz fundamental-mode crystal (e.g., SaRonix-eCera FL2500029) via X1/X2, generates a non-PLL 25 MHz LVCMOS reference (REF_Out), and provides three distinct output banks with differential LVDS (QCx±), single-ended LVCMOS (QAx/QBx), and configurable drive strength-all meeting Ethernet timing integrity requirements including sub-1 ps integrated jitter and <50 ps inter-output skew within banks.

Key Specifications

Pinout & Package

Package: 32-pin 5×5 mm TQFN (ZH), RoHS-compliant, with exposed thermal pad for enhanced power dissipation in high-density Ethernet PHY clocking applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar frequency synthesizer applications.

Compared with Si5338A-D-GM and ICS8430I-01T, the PI6LC4840ZHE uniquely balances fixed-Ethernet-frequency optimization, hardware-configurable outputs, and non-PLL reference generation-making it ideal for cost-sensitive, firmware-light 10GbE switch designs where crystal-referenced stability is prioritized over programmability.

Availability

PI6LC4840ZHE is available at Aetrix Electronics and suitable for 10GbE switch PHY clocking, multi-rate Ethernet line cards, industrial Ethernet controllers, and optical transport network framer applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for PI6LC4840ZHE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, interface, and signal integrity solutions for communications and computing markets.

The PI6LC4840ZHE belongs to Pericom's low-phase-noise clock synthesizer product line, engineered specifically for Ethernet physical layer timing-emphasizing jitter performance, multi-output flexibility, and crystal-referenced stability over general-purpose programmability.

FAQ

What crystal specifications are required for PI6LC4840ZHE?

The PI6LC4840ZHE requires a 25 MHz fundamental-mode parallel-resonant crystal with 18 pF load capacitance, ≤50 Ω ESR, and ≤0.65 mW drive level. Recommended part is SaRonix-eCera FL2500029. External load capacitors C1/C2 should be 27 pF each for CL=18 pF crystals, adjustable per PCB layout.

How is output frequency selected across the three banks?

Frequency selection is controlled by Mode[2:0] pins: Bank A (QA0–QA2) supports 25/50 MHz via pin strapping; Banks B (QB0–QB2) and C (QC0±–QC2±) are fixed at 125 MHz. Table 4 in the datasheet defines all 8 mode combinations-including default state (010) enabling 25 MHz on QA0 and 125 MHz on QC0–QC2.

Can PI6LC4840ZHE generate 25 MHz LVDS outputs?

No. The PI6LC4840ZHE does not support 25 MHz LVDS outputs. Its LVDS outputs (QC0±–QC2±) are fixed at 125 MHz. The 25 MHz output is available only as LVCMOS (REF_Out) or pin-selectable LVCMOS (Bank A). No internal divider or output stage converts REF_Out to LVDS.

What is the purpose of separate VDDA and VDD supply pins?

VDDA powers the analog VCO and PLL circuitry, while VDD supplies digital logic and output buffers. This separation minimizes noise coupling from digital switching into the sensitive analog timing path-critical for achieving sub-1 ps integrated phase jitter. Both require 3.3 V ±5%, but must be decoupled independently per datasheet layout guidelines.