Diodes Incorporated PI6LC4840ZHEX

Overview

PI6LC4840ZHEX from Pericom Semiconductor is a crystal-to-LVDS/LVCMOS frequency synthesizer with LC-based VCO architecture, designed for low-phase-noise Ethernet clocking. It supports 25MHz crystal input and delivers three banks of outputs: Bank A (3× 25/50MHz LVCMOS), Bank B (3× 125MHz LVCMOS), and Bank C (3× 125MHz LVDS), plus one dedicated 25MHz LVCMOS reference output without PLL. Operating at 3.3V ±5% over –40°C to +85°C, it targets high-integrity 1G/10G Ethernet PHY timing.

For engineers reviewing the PI6LC4840ZHEX datasheet, PI6LC4840ZHEX pinout, PI6LC4840ZHEX application, or PI6LC4840ZHEX equivalent, key selection criteria include integrated phase jitter (≤1ps @12kHz–20MHz for 125MHz outputs), bank-selectable output frequencies, LVDS/LVCMOS coexistence, and industrial-grade thermal stability - all critical for multi-protocol switch/router clock trees.

Technical Context

The PI6LC4840ZHEX implements an LC-VCO-based PLL architecture with programmable division ratios (÷4, ÷10, ÷20) to generate 125MHz from a 25MHz fundamental crystal. Its analog core (VDDA) is independently biased to minimize noise coupling into the VCO and output buffers.

Three independent output banks are powered by separate supply rails (VDDO_QA/QB/QC), enabling voltage-domain isolation and flexible termination. Mode pins (Mode_0/1/2) configure both frequency selection and output enable per bank, with default state (0*1*0*) delivering 25MHz on QA0/QA1 and 125MHz on QC0/QC1.

Key Specifications

Pinout & Package

Package: 32-pin 5×5mm TQFN (ZH code), RoHS-compliant and halogen-free. Exposed thermal pad recommended for soldering to PCB ground plane to maintain junction temperature under full load.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar frequency synthesizer applications.

Compared with Si5338A-D-GM and ICS8430I-01T, the PI6LC4840ZHEX uniquely combines crystal input, triple-bank output flexibility, and industrial-grade jitter performance in a single fixed-function device - reducing BOM count and eliminating configuration overhead in Ethernet PHY-centric designs.

Availability

PI6LC4840ZHEX is available at Aetrix Electronics and suitable for 10GBASE-T Ethernet PHY clocking, multi-port switch timing, industrial gateway synchronization, and optical line terminal control requiring stable component supply and long-term lifecycle support.

Supply support for PI6LC4840ZHEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface solutions for communications and computing infrastructure.

The PI6LC4840 belongs to Pericom's low-phase-noise clock synthesizer product line, engineered specifically for Ethernet physical layer timing compliance - emphasizing jitter minimization, multi-protocol output flexibility, and robust industrial operation.

FAQ

What crystal specifications are required for reliable PI6LC4840ZHEX operation?

The PI6LC4840ZHEX requires a 25MHz parallel-resonant crystal with 18pF load capacitance, ≤50Ω ESR, and ≤0.65mW drive level. Recommended part is SaRonix-eCera FL2500029. External load capacitors C1/C2 = 27pF are suggested for CL=18pF crystals; layout-dependent fine-tuning may be needed to achieve target ppm accuracy.

Can PI6LC4840ZHEX generate 25MHz and 125MHz simultaneously on different banks?

Yes. In Mode[2:0] = 001, Bank A outputs 25MHz on QA0, Bank B outputs 125MHz on QB0–QB2, and Bank C outputs 125MHz on QC0±–QC2±. The REF_Out pin simultaneously delivers a 25MHz LVCMOS signal independent of PLL operation - enabling concurrent use of fundamental and multiplied clocks.

How does the PI6LC4840ZHEX handle power supply noise on its output banks?

Each output bank (A/B/C/REF) has dedicated power supply pins (VDDO_QA/QB/QC/VDDO_REF) with independent decoupling paths. This architecture isolates switching noise between banks; measured PSRR exceeds –50dB for LVDS outputs under 10kHz–15MHz modulation, preventing supply ripple from modulating the VCO or output buffers.

Is the MR (Master Reset) pin necessary for normal operation?

The MR pin is not required for normal operation but is strongly recommended for deterministic startup. When asserted low, it forces all LVCMOS outputs to logic low and LVDS outputs to defined differential states (QCx+ low, QCx– high), preventing metastability or undefined clock edges during power ramp. Internal weak pull-up on MR is insufficient for robust reset sequencing.